Can I have a mode where some of that 128M is never flushed to RAM?
For example, I'd quite like my disk encryption key to never end up in RAM - it's much harder to steal from inside a running CPU...
AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
111–120 of 221 posts
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#112Earlier quoted context omitted.
Or buy an X3D that's homogeneous, like the 5800X3D or upcoming 7800X3D. I have no idea why AMD made the 7950X3D be this weird 50/50 split. Why not make both CCDs have 3D V-cache and make it the true halo part it should be? Then cut costs with the 7900X3D?
So they can sell us a 7990X3D 6 months down the line for $1000
Does AMD have a history of this blatant of a move? That would be an Nvidia level of arrogance.
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#113AnandTech sees some intriguing regressions on certain benchmarks, https://www.anandtech.com/show/18747/the-amd-ryzen-9-7950x3d... ( "CPU Benchmark Performance: Simulation" ) Worst is Factorio, which is down -47% against the 5800X3D (a previous-generation CPU that also uses stacked L3 cache), on the benchmark "10K trains". Wonder what's going on there? - "We would have expected higher performance in our Factorio bench…
Depends on good scheduling choices since some threads benefit from the higher clocked CCD and others benefit from the higher cache CCD. Sounds like AMD is using a lookup table style scheduler on windows. I believe the system mostly schedules the higher clock CCD by default.
Similar problem to big.little but less differentiation between the cores. It's big.big. Kind of a mess outside of the primary use case that is games on windows with a static tuned scheduler.
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#114"AMD Ryzen 9 7950X3D Linux Performance" https://www.phoronix.com/review/amd-ryzen9-7950x3d-linux "AMD Ryzen 9 7950X3D Desktop CPU Review Roundup" https://videocardz.com/150677/amd-ryzen-9-7950x3d-desktop-cp...
the Linux test leaves me quiet confused how to pick my next linux gaming cpu. On the one hand side Gamers Nexus is making a point [0] (there are on/off performance charts later in the video) why it is super important to install the latest windows drivers + special windows gaming software to make use of the heterogeneous architecture. On the other hand side the linux tests are much better then I would expected since i…
Keep the one you have now and pick a better GPU?
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#115Earlier quoted context omitted.
It's the CPU scheduler. You can easily avoid this by just not buying an X3D variant. Recent Intel CPUs can have the same problem where processes get assigned to the efficiency cores instead of performance cores if the right scheduler isn't used (like by using Windows 10 or an old Linux distro without explicit support)
Or buy an X3D that's homogeneous, like the 5800X3D or upcoming 7800X3D. I have no idea why AMD made the 7950X3D be this weird 50/50 split. Why not make both CCDs have 3D V-cache and make it the true halo part it should be? Then cut costs with the 7900X3D?
There was some outcry about 5800X3D having lower clocks. This was there "we solved the clock speed problem with a v-cache SKU" move, which was promised somewhere... And I guess, if you use games as a primary load and they fix their scheduler, then it seems to work for both cases.
But I don't like this franken chip. I would much rather 7800X3D. But then, I don't play games, so the scheduler would just be terrible.
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#116> To make sure gaming workloads find the right CCD, AMD has implemented a high degree of software-level control, in the form of its 3D Vertical Cache Optimizer Driver, which is included with the latest version of AMD Chipset Software. This driver ensures that workload from games are directed to the CCD with the 3D Vertical Cache using dynamic "preferred cores" flagging for the Windows OS scheduler. Yeah, what about g…
I already do this by hand with `taskset` when it's important. I would totally exploit this asymmetry.
Yeah, manually is one method, if you figure out some workload benefits from cache more.
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#117Related and also interesting: Ryzen 7950X3D with One CCD Disabled - The 7800X3D Preview https://www.techpowerup.com/review/ryzen-7800x3d-performance...
> Where AMD X3D is taking the wrecking ball to Intel is power consumption. Our simulated Ryzen 7 7800X3D is one of the most energy-efficient CPUs we ever tested. In gaming it consumes 44 W on average, while the competition is wasting a ton of energy to achieve the same FPS: 13900K (143 W), 13700K (107 W), 13600K (89 W)—all more than twice the power usage than AMD's new gaming gem. Wow. I don't needed such CPU now, bu…
Yeah, I’m pretty happy with my older and slower 3600, but after the preview I thought this might be an interesting upgrade in the future after prices for AM5 boards, DDR5, and the CPUs fall.
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#118Earlier quoted context omitted.
Is there a point to going beyond 60 updates/s in Factorio? Because if not the system seems to be doing the correct thing and using less power. I hope AMD isn’t causing higher power usage for all users just to game some benchmarks!
It's not like the CPU looks at the FPS to decide how to clock. Factorio has extremely variable CPU demand as your base grows.
Modern CPU and scheduler combos will in fact try to do that or, at least, do something that has that as a second order effect. They’ll try to run the CPU at a speed that evens out regular bursts into steady loads, on the lowest power core on which that’s possible to do.
Edit: although, for that to work for this workload Factorio itself would need to be updating at a steady 60 updates/s, which I guess is not actually the case here…
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#119Earlier quoted context omitted.
An OS can easily run an app on each for a few milliseconds, look at the performance counters to see which ends up with more instructions executed, and then move the task to where it performs best. From time to time, it can retry the test, because software frequently changes what it spends time doing.
But apps like factorio are extremely dynamic, so thats either going to be flakey or its going to spend a lot of time/energy bouncing the process between cores. I wouldn't be too worried about this personally, as configuring the few really sensitive apps with ProcessLasso or Aniancy is pretty easy.
I feel that with good statistics this could be done in the OS scheduler successfully. But it’s not my area of expertise.
Re: AMD releases a new flagship CPU for consumer market with 128M of L3 Cache
#120Silly question: what constrains cache sizes? What prevents just making them bigger and bigger?
Cache size is constrained by different things at different levels.
Cache uses 6 transistors per bit while normal RAM uses 1 transistor and 1 capacitor. You can buy a LOT more RAM per dollar than you could buy cache. This has been further exacerbated by poor SRAM scaling with each new fabrication node. It's usually 20-30% instead of 60-80% for other transistors and is actually 0% for TSMC's upcoming N3 node. AMD chose to fab their RDNA 3 GPU die on 5nm, but their SRAM dies on 6nm because the cost savings were much bigger than the effect of a slightly larger die.
DRAM typically has a maximum cycle speed of around 300-500MHz due to the capacitors having more restrictive charge/discharge rates (when you see something like 6400MT/s, that's not random access speed, but is instead the aggregate speed of slowly reading thousands of cells in parallel at one time into a cache then quickly sending the results over the wire).
Once you move away from bulk storage into high-performance caches, you have to discuss speed, latency, and associativity. As cache gets bigger, keeping lookup times low requires more and more transistors to control the cache and keep it coherent with both the CPU/threads and main memory. If you want to make that controller smaller, it will mean lowering clockspeeds, altering latencies, changing associativity, etc. At a physical level, faster caches will require higher-performance transistors which require more die space and power per transistor too.
Sometimes, the tradeoffs aren't what you might expect. A great example is AMD moving from 64kb of I-cache in Zen1 to 32kb I-cache in Zen 2, 3, and 4 because they found the tighter latencies were more important in their uarch than the higher hit rate.
There's a further constraint for AMD's 3D chip where the cache reduces heat transfer forcing lower CPU clockspeeds. Unfortunately there's not much room on the substrate to add the cache beside the CPU. Infinity Cache on RDNA3 also uses a significant portion of it's die space for the super-fast interconnect with the GPU die. I suspect a similar thing happens here too.