What's different about next-gen transistors • Hacker News Board

Re: What's different about next-gen transistors

#21

Post by agumonkey » Fri, Oct 21, 2022, 8:18 PM UTC

B1FF_PSUVM wrote: post #7

Rabbit hole diving on the makers of the machines that make chips: https://semiengineering.com/entities/asml/ https://en.wikipedia.org/wiki/ASM_International https://www.asml.com/en/company/about-asml/history From the last one, ca. 1988 ASML was failing badly: "But in a market of fierce competition and many suppliers, the small unknown company from the Netherlands couldn’t catch a break. ASML had few customers and was…

Interesting how the present came from a very fragile, almost non happening past.

A lot less critical, I've read that Olivetti vanished from the industry due to random finance wars between France and Belgium with some bank (which bought the company not long before) crashing and thus cutting money right at the moment where PC were taking off.

Re: What's different about next-gen transistors

#22

Post by inasio » Fri, Oct 21, 2022, 8:25 PM UTC

justinlloyd wrote: post #18

There's a lot coming down the pipe in term of next-gen components in the SOI and 3D subthreshold world, ULP (ultra-low power), MEMS (pretty much everything you find in your phone these days, outside of the CPU itself), 3D integration, the problem is summarizing it in a neat little comment. Memristors are huge, and are going to be, huge-er still. World changing huge. Which ties in to new analogue design techniques. 3D…

Together with memristors, in-memory compute is likely going to be a big deal. It's already here in some forms, see e.g. Content Addressable Memory in high end networking gear.

Re: What's different about next-gen transistors

#23

Post by Hikikomori » Fri, Oct 21, 2022, 8:29 PM UTC

Aardwolf wrote: post #10

Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer. So how are the multiple layers done, if light is shined on the surface, how do you reach the other…

https://youtu.be/NGFhc8R_uO4

Re: What's different about next-gen transistors

#24

Post by modeless » Fri, Oct 21, 2022, 8:43 PM UTC

justinlloyd wrote: post #18

There's a lot coming down the pipe in term of next-gen components in the SOI and 3D subthreshold world, ULP (ultra-low power), MEMS (pretty much everything you find in your phone these days, outside of the CPU itself), 3D integration, the problem is summarizing it in a neat little comment. Memristors are huge, and are going to be, huge-er still. World changing huge. Which ties in to new analogue design techniques. 3D…

Memristors aren't huge yet, are they? Don't they have wear issues? Who is working on them?

Re: What's different about next-gen transistors

#25

Post by robotburrito » Fri, Oct 21, 2022, 8:45 PM UTC

Chip War is a fantastic book about the history of this industry. I would recommend it highly for some background information.

Re: What's different about next-gen transistors

#26

Post by ABeeSea » Fri, Oct 21, 2022, 8:49 PM UTC

justinlloyd wrote: post #18

There's a lot coming down the pipe in term of next-gen components in the SOI and 3D subthreshold world, ULP (ultra-low power), MEMS (pretty much everything you find in your phone these days, outside of the CPU itself), 3D integration, the problem is summarizing it in a neat little comment. Memristors are huge, and are going to be, huge-er still. World changing huge. Which ties in to new analogue design techniques. 3D…

I feel like memresistors have been hyped since HP tried to use it to save their business from 2007-2015. Nothing ever came from it from HP at least. Have there been new developments that make it more likely to be viable?

Re: What's different about next-gen transistors

#27

Post by justinlloyd » Fri, Oct 21, 2022, 9:24 PM UTC

ABeeSea wrote: post #26

justinlloyd wrote: post #18

There's a lot coming down the pipe in term of next-gen components in the SOI and 3D subthreshold world, ULP (ultra-low power), MEMS (pretty much everything you find in your phone these days, outside of the CPU itself), 3D integration, the problem is summarizing it in a neat little comment. Memristors are huge, and are going to be, huge-er still. World changing huge. Which ties in to new analogue design techniques. 3D…

I feel like memresistors have been hyped since HP tried to use it to save their business from 2007-2015. Nothing ever came from it from HP at least. Have there been new developments that make it more likely to be viable?

A lot of technology that's out at the fringes will often be hyped up by a marketing department. It is the culinary equivalent of telling everyone how awesome the soup is going to taste just as the cook is returning from the grocery store with the unprepared, raw ingredients. We're edging closer to the "needs seasoning." There's always some company trying to sell something that doesn't really exist in a production form, and then 10 years or 20 years later, it is so in the background we don't even think of it anymore. You know how pricing works? Multiply by ten for every step from cost of raw materials to a commercial product in your hand? 10x to turn the raw materials in components. 10x to turn components in to a product. 10x to move the product to the store. 10x to sell it to you as an item you can use. Same kind of idea when it comes to technology research, but in terms of time. Six months of research becomes five years of development becomes ten years of commercialization becomes twenty years of "it's everywhere."

Re: What's different about next-gen transistors

#28

Post by thunderbird120 » Fri, Oct 21, 2022, 10:06 PM UTC

modeless wrote: post #24

justinlloyd wrote: post #18

There's a lot coming down the pipe in term of next-gen components in the SOI and 3D subthreshold world, ULP (ultra-low power), MEMS (pretty much everything you find in your phone these days, outside of the CPU itself), 3D integration, the problem is summarizing it in a neat little comment. Memristors are huge, and are going to be, huge-er still. World changing huge. Which ties in to new analogue design techniques. 3D…

Memristors aren't huge yet, are they? Don't they have wear issues? Who is working on them?

They're definitely not huge right now and I haven't seen any viable paths toward them becoming a big thing any time in the near future. There's barely any work being put into them relative to other stuff in the field. HP made some big claims years back but have totally failed to deliver anything and I haven't heard anything about the technology in years.

Re: What's different about next-gen transistors

#29

Post by martincmartin » Fri, Oct 21, 2022, 10:16 PM UTC

So carbon atoms are spaced about 0.15 nm apart in carbon metal. So a 3nm process is about 20 carbon atoms.

Impressive.

Re: What's different about next-gen transistors

#30

Post by mjgerm » Fri, Oct 21, 2022, 10:49 PM UTC

hinkley wrote: post #2

Are we ever going to circle back to the notion of creating circuits that can hold more than 2 states? We seem to be doing that for SSDs but not for logic. Or has the space already been explored and there's nothing there?

Roughly speaking, an N-level digital logic system requires O(N) transistors in order to buffer/force a signal into one of N states, but only performs O(log(N)) more work with them relative to binary.

Without the buffering step, you'll eventually get the middle logic levels drifting (e.g. your "1"s become "0"s or "2"s). Binary gets this for "free" because there's no middle states; this doesn't apply just to a simple buffer, similar details apply to the implementation of all other gates (many of which are rather awkward to implement).

Analog works out for rough calculations because you can skip the buffering process, at the expense of having your calculation's precision limited by the linearity of your circuit.

SSDs are more of a special case, because to my knowledge they're not really doing work on multi-level logic outside of the storage cells. They pump current in on one axis of a matrix, read it out on the other, and then ADC it back to binary as fast as possible before doing any other logic.

Random sidebar: I don't see any constraint like this for mechanical computers, so a base-10 mechanical computer doesn't strike me as any more unreasonable than a base-2 mechanical computer (i.e. slop and tolerance is independent of gear size). In fact, it might be reasonable to say you should use the largest gears that the technology of your time can support (sorry Babbage).