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What's different about next-gen transistors

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Re: What's different about next-gen transistors

#11

Post by hinkley »

bigmattystyles wrote: post #3
hinkley wrote: post #2

Are we ever going to circle back to the notion of creating circuits that can hold more than 2 states? We seem to be doing that for SSDs but not for logic. Or has the space already been explored and there's nothing there?

https://en.wikipedia.org/wiki/Ternary_computer#History

I'm aware of ternary computers.

What I was trying to say is that there are things we don't do because they're hard or we don't know how, and there are things that we don't do because we've proven they don't work.

Ternary does have some cool features though.

Re: What's different about next-gen transistors

#12

Post by spyremeown »

Aardwolf wrote: post #10

Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer. So how are the multiple layers done, if light is shined on the surface, how do you reach the other…

There are "wells" to tap the components into. You just add successive layers in a very smart way.

Re: What's different about next-gen transistors

#13

Post by variadix »

Aardwolf wrote: post #10

Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer. So how are the multiple layers done, if light is shined on the surface, how do you reach the other…

It’s built from the bottom up in layers (at least traditionally, I’m not sure how the newer 3D structures for memory are constructed). The bottom layer of silicon substrate is covered in an oxide and etched selectively by photoresist and masking. Further layers are connective layers of metal lines insulated by oxide, with vias connecting metal layers to one another. The same oxide deposition, photoresist, expose, etch process is used for each layer.

Re: What's different about next-gen transistors

#14

Post by ThrowawayR2 »

Aardwolf wrote: post #10

Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer. So how are the multiple layers done, if light is shined on the surface, how do you reach the other…

You can only ever reach exposed surfaces. This means a very complex sequence of adding and removing layers to expose/hide things so that the currently exposed surface features are what you want to change in the current processing step.

The Wikipedia article on CMOS has a very nice illustration of the basic steps of this process: https://en.wikipedia.org/wiki/CMOS#/media/File:CMOS_fabricat... Current processes are much more complex than even that.

Re: What's different about next-gen transistors

#15

Post by 202210212010 »

jlokier wrote: post #5
hinkley wrote: post #2

Are we ever going to circle back to the notion of creating circuits that can hold more than 2 states? We seem to be doing that for SSDs but not for logic. Or has the space already been explored and there's nothing there?

Memristor and analogue processors to accelerate ML are doing this. Neural networks are ok with operations on noisy, analogue states. Analogue operations such as op-amp multiplication are more power hungry than individual digital gates, but some are less power hungry than digital multipliers which use thousands of gates. For digital, noise-free logic, it's generally more power efficient and physically simpler to have…

> Memristor and analogue processors to accelerate ML are doing this. Neural networks are ok with operations on noisy, analogue states. Analogue operations such as op-amp multiplication are more power hungry than individual digital gates, but some are less power hungry than digital multipliers which use thousands of gates.

I checked Mouser just now and memristors are not in stock: https://www.mouser.com/c/?q=memristor

If we are talking about imaginary components, then I think quantistors will change everything.

Re: What's different about next-gen transistors

#16

Post by mattbillenstein »

variadix wrote: post #13
Aardwolf wrote: post #10

Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer. So how are the multiple layers done, if light is shined on the surface, how do you reach the other…

It’s built from the bottom up in layers (at least traditionally, I’m not sure how the newer 3D structures for memory are constructed). The bottom layer of silicon substrate is covered in an oxide and etched selectively by photoresist and masking. Further layers are connective layers of metal lines insulated by oxide, with vias connecting metal layers to one another. The same oxide deposition, photoresist, expose, etc…

Haven't worked in the space in more than 15 years, but as I recall there were dozens of masks - maybe upwards of 50 - when I was doing ASIC.

And I believe there were steps to flatten and I believe effectively sand the surface flat after some layers.

Re: What's different about next-gen transistors

#17

Post by drexlspivey »

b3orn wrote: post #4
hinkley wrote: post #2

Are we ever going to circle back to the notion of creating circuits that can hold more than 2 states? We seem to be doing that for SSDs but not for logic. Or has the space already been explored and there's nothing there?

Nothing I can link you, but I read about some companies trying to bring back analog computers for machine learning purposes.

Relevant Veritasium: https://youtu.be/GVsUOuSjvcg and https://youtu.be/IgF3OX8nT0w

Re: What's different about next-gen transistors

#18

Post by justinlloyd »

There's a lot coming down the pipe in term of next-gen components in the SOI and 3D subthreshold world, ULP (ultra-low power), MEMS (pretty much everything you find in your phone these days, outside of the CPU itself), 3D integration, the problem is summarizing it in a neat little comment. Memristors are huge, and are going to be, huge-er still. World changing huge. Which ties in to new analogue design techniques. 3D integration, which we have had for a decade, is at the tipping point as we move to new nodes and start making monolithic integration a thing. Ultra low power energy efficient compute at the edge, we're talking consuming less power in a year than it takes me to think about what I want to say when writing this comment right now. On-die microfluidic cooling for 3D dies is starting to appear. On-die sensors for new camera tech. We're edging up to a point where multiple sensors and/or a camera, compute, model inference and mesh network connectivity all exist on a single die.

Re: What's different about next-gen transistors

#19

Post by JumpCrisscross »

variadix wrote: post #13
Aardwolf wrote: post #10

Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer. So how are the multiple layers done, if light is shined on the surface, how do you reach the other…

It’s built from the bottom up in layers (at least traditionally, I’m not sure how the newer 3D structures for memory are constructed). The bottom layer of silicon substrate is covered in an oxide and etched selectively by photoresist and masking. Further layers are connective layers of metal lines insulated by oxide, with vias connecting metal layers to one another. The same oxide deposition, photoresist, expose, etc…

> oxide deposition, photoresist, expose, etch process is used for each layer

Would note that since FinFETs, deposition occurs from the side as well as top.

Re: What's different about next-gen transistors

#20

Post by pclmulqdq »

Aardwolf wrote: post #10

Random semi related question about chip making: AFAIK CPU's have multiple layers, not just a single silicon layer of transistors. And also, making transistors involves doping the silicon with other elements. And lithography is about shining a laser through a mask. And all this starting from an already cut silicon wafer. So how are the multiple layers done, if light is shined on the surface, how do you reach the other…

Each wafer has only one layer of transistors. They then have many layers of wiring on top. They go through semiconductor manufacturing with one layer of transistors.

For each layer of metal, they go through several steps of deposition of insulator, masking, etching, deposition of metal (often in several passes now), grinding or etching that, and then covering it all up with more insulator and grinding that layer down to produce a smooth surface for the next layer.

Once the chips are complete, 3D stacking is a packaging process. It involves grinding the backsides of the chips down until they are very thin and attaching the dies together using vias that run through the thin remaining silicon layer.

EDIT: Flash memory today has multiple stacked doped silicon layers, but it is a special process that is largely unsuitable for logic.

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