F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3 • Hacker News Board

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#11

Post by benrow » Fri, Sep 16, 2022, 9:20 AM UTC

zargon wrote: post #6

If only it were possible to buy such chips.

I received an ice40 hx8k breakout board two days ago, my first foray into FPGA. Looking forward to playing with IceStorm over the weekend.

Stock for these seems OK, at least in the UK where I am based. It was ordered from Farnell. Mouser also have them in stock, but the situation may be different in other countries.

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#12

Post by lnsru » Fri, Sep 16, 2022, 9:28 AM UTC

Are these tools able to handle the Xilinx blocks like BUFGMUX_CTRL? Or I should still have fun by myself? That makes the difference. Writing plain VHDL and constraints is the smallest pain point for me.

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#13

Post by GeneT45 » Fri, Sep 16, 2022, 10:05 AM UTC

vardump wrote: post #4

The sorry landscape of open source FPGA tools has kept me away from them whenever possible. Programmable IO such as RP2040 (Raspberry Pi Pico) are eating a tiny (but increasing) part of FPGA lunch. Altera (well, Intel) and Xilinx (well, AMD) are just hurting themselves by not working to move towards an open ecosystem. Edit: Oh, so AMD is partially behind F4PGA. Well, points for them, perhaps it's time to move away fr…

I avoid Altera altogether because Intel doesn't seem to care much about them. Quartus has either been abandoned, or received the barest minimum updates. Setting up a new system is an adventure in patches & workarounds.*

*It's possible that some of this has been remedied, I gave up on them a few years ago and haven't checked back...

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#14

Post by dayjaby » Fri, Sep 16, 2022, 11:18 AM UTC

lnsru wrote: post #12

Are these tools able to handle the Xilinx blocks like BUFGMUX_CTRL? Or I should still have fun by myself? That makes the difference. Writing plain VHDL and constraints is the smallest pain point for me.

Yes, you can use existing blocks and IPs.

E.g. if you use the f4pga+migen+LiteX stack, this looks like this in the end: https://github.com/enjoy-digital/litex/blob/d36f98bf45c20e2f...

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#15

Post by le-mark » Fri, Sep 16, 2022, 12:09 PM UTC

buildbot wrote: post #2

It's an extremely nice breath of fresh air to use open source tools to compile an FPGA design.

Yes, can anyone comment on the xilinx 7 series support? Is bitstream 100% reversed today?

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#16

Post by bhedgeoser » Fri, Sep 16, 2022, 12:29 PM UTC

How is an fpga different from an emulator? From what I've read it looks like just a microcontroller that emulates a cpu chip.

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#17

Post by infinityio » Fri, Sep 16, 2022, 12:35 PM UTC

bhedgeoser wrote: post #16

How is an fpga different from an emulator? From what I've read it looks like just a microcontroller that emulates a cpu chip.

I think the critical difference is that the 'emulation' is effectively done in hardware instead of software, so designs can be clocked much higher than traditional emulation (GHz+ speeds)

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#18

Post by trebligdivad » Fri, Sep 16, 2022, 12:36 PM UTC

bhedgeoser wrote: post #16

How is an fpga different from an emulator? From what I've read it looks like just a microcontroller that emulates a cpu chip.

No, an FPGA is a lot lower level thing; it's basically a bag full of small logic blocks, each one that can only do a very small logic function (something like a 16 entry table lookup?) and some blocks of RAM and IO. The FPGA user has to figure out how to wire those blocks up to do what you want; you can build a micro with it, but you can build most other logic systems as well.

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#19

Post by sjkelly » Fri, Sep 16, 2022, 12:44 PM UTC

le-mark wrote: post #15

buildbot wrote: post #2

It's an extremely nice breath of fresh air to use open source tools to compile an FPGA design.

Yes, can anyone comment on the xilinx 7 series support? Is bitstream 100% reversed today?

There are some phys missing like PCIe.

Re: F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3

#20

Post by jpm_sd » Fri, Sep 16, 2022, 1:09 PM UTC

vardump wrote: post #4

The sorry landscape of open source FPGA tools has kept me away from them whenever possible. Programmable IO such as RP2040 (Raspberry Pi Pico) are eating a tiny (but increasing) part of FPGA lunch. Altera (well, Intel) and Xilinx (well, AMD) are just hurting themselves by not working to move towards an open ecosystem. Edit: Oh, so AMD is partially behind F4PGA. Well, points for them, perhaps it's time to move away fr…

The RP2040 is an example of a "microcontroller", a low-power processor with onboard program storage (typically Flash these days), and a bunch of handy peripherals (UART, I2C, PWM etc.) in a single small package. This is a modern type with 32 bit ARM processor but microcontrollers have been used by the millions, for decades(!) in consumer products, automotive hardware, etc. Not too many 8 bit machines used by hobbyists today, but 8051 and PIC and AVR live on in numerous product lines.

The RP2040 is definitely not pioneering here. More of a well-marketed "me too" device IMHO.

FPGAs, on the other hand, have always been for specialized applications. High speed signal processing for imaging, sonar, or radar. Boundary-pushing network interface design. That kind of thing. They use a ton of power and developers are hard to find.