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Forth Inventor Chuck Moore's $20 144 core CPU now in full production

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Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#91

Post by bisrig »

mindslight wrote: post #89
bisrig wrote: post #52

Earlier quoted context omitted.

As an FPGA guy, I want to ask this - what software programming languages, models, etc. exist to support the description of fundamentally concurrent processing, whether task-parallel, data-parallel, hybrid, or "other" (whatever that may be) that will allow for the supplanting of HDLs? I know that there's been long-standing efforts to do C-to-HDL but to my knowledge the successes of this approach have been limited to r…

PI calculus/actor model/'erlang style' concurrency. In (synthesizable) verilog, you have tiny state machines communicating via explicit channels (clock+wires+buses), and functions that get turned into gates. A higher level language would give you ideal channels (mapping onto fixed hardware channels or synthesized to HDL). Depending on their complexity, the functions at each state-node would also be transformed to use…

Do you have links to any tutorial, intros or such for the list that you enumerated above? I am very much in appreciation of your (and everyone else's) feedback - learning of a number of new options and approaches that are worth further research.

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#92

Post by thesz »

bitcracker wrote: post #83
thesz wrote: post #77

Earlier quoted context omitted.

I protyped dynamic dataflow machine which (in theory) could be scaled to hundreds of cores (corelets - something very small which does not have even jump command). In my experiments readying information to be sent accounts for hefty 30%+ of code. http://thesz.mskhug.ru/svn/hhdl/previous/HSDF/CoreletTest.hs The link above contains some simple "Hello, world!" program, in five "big instructions" which contains 21 corele…

> In my experiments readying information to be sent accounts for hefty 30%+ of code. Unfortunately I don't have time to dive into your design but AFAIK the GA144 doesn't need 30% preparation code because every instruction can be executed immediately by neighbor nodes. That means (correct me if I am wrong) if core X has to evaluate a Forth function of say five arguments then it could pass all five arguments to its nei…

I think you're wrong about many arguments for command send to other core.

You can send a word, ie, "big command" composed from four MISC command. One of MISC commands in "big command" can retrieve data from other core.

So most of the time you will wait to send a command or to receive some data.

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#93

Post by mindslight »

bisrig wrote: post #91
mindslight wrote: post #89

Earlier quoted context omitted.

PI calculus/actor model/'erlang style' concurrency. In (synthesizable) verilog, you have tiny state machines communicating via explicit channels (clock+wires+buses), and functions that get turned into gates. A higher level language would give you ideal channels (mapping onto fixed hardware channels or synthesized to HDL). Depending on their complexity, the functions at each state-node would also be transformed to use…

Do you have links to any tutorial, intros or such for the list that you enumerated above? I am very much in appreciation of your (and everyone else's) feedback - learning of a number of new options and approaches that are worth further research.

I haven't been in the hardware world for a while, so I don't have a great answer to your question. For concrete embedded systems tools, I'd look to see what springs up around chips like the OP (I think Parallax made a massively parallel chip a while back, too?). Hardware system design is already all about explicitly decomposed parallelism. The problems to be solved are really from the software perspective of not caring about how concurrent resources are automatically allocated, as long as the constraints are met. If you're looking to learn how to think about parallelism in that manner, I would learn to program in a popular high level language such as Erlang.

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#94

Post by calebmpeterson »

tomjen3 wrote: post #64
calebmpeterson wrote: post #48

Earlier quoted context omitted.

You've piqued my curiosity; could you elaborate please?

I shall try, but this stuff gets really hairy, really really fast. Von Neumann architecture is what almost all computers use today: you have (very roughly) an ALU (arithmetic logic unit) hooked up to a memory bank which stores both program data and the instructions the program consist of. Now you can add a couple of cores to that, but you pretty soon start to run into problems -- threads which try to access the same…

That wasn't a "try" - that was a success. Thank you!

If I may attempt a paraphrase: CPU caches stop being a bandage for slow access to RAM and become a valuable first class citizen for each core of the CPU when coupled with the actor model.

Did I understand you correctly? Again, thank you.

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#95

Post by derleth »

aidenn0 wrote: post #90
derleth wrote: post #62

Earlier quoted context omitted.

OTOH, LLVM is, if anything, a register machine, so as to better map to the register machines we're implementing in hardware right now.

ACtually LLVM isn't a virtual machine, it's a compiler intermediate representation.

And when JVM bytecodes are compiled to machine code by the hotspot optimizer, what is the JVM?

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#96

Post by Poyeyo »

csmeder wrote: post #11
neopanz wrote: post #5

I think the only thing Chuck is missing is a few 20-somethings hackers, bent on solving an 'impossible' problem with his chips.

That's why I'm posting it here. Some possible ideas ==================== - Sound processing (think 144 cores preforming Fourier Transforms) - Pico Satellites (This chip has a surprisingly extreme low power requirement). - Wireless communication (small power requirement means small batteries) - Computer Vision processing. Imagine toys or tools that can process visual information faster than an Xbox. - Basically anythi…

Video-games?

Can this replace a physics dedicated processor? What about latency?

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#97

Post by tomjen3 »

calebmpeterson wrote: post #94
tomjen3 wrote: post #64

Earlier quoted context omitted.

I shall try, but this stuff gets really hairy, really really fast. Von Neumann architecture is what almost all computers use today: you have (very roughly) an ALU (arithmetic logic unit) hooked up to a memory bank which stores both program data and the instructions the program consist of. Now you can add a couple of cores to that, but you pretty soon start to run into problems -- threads which try to access the same…

That wasn't a "try" - that was a success. Thank you! If I may attempt a paraphrase: CPU caches stop being a bandage for slow access to RAM and become a valuable first class citizen for each core of the CPU when coupled with the actor model. Did I understand you correctly? Again, thank you.

Well you could do that today if you as a programmer could manually tell the system "please load addr x, y and z into the cache".

But if the cores of the CPU starts to communicate with the actor model then you wouldn't be using the memory close to the cores as a cache but as a storage area for messages that haven't been sent/processed yet as well as possible for thread local storage.

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#98

Post by watmough »

pnathan wrote: post #82
ChuckMcM wrote: post #9

Well if you ever wanted to be 'out there' Chuck's processor would be a great place to start. Chuck Moore invented Forth and has been building machines that can run Forth efficiently for years. Think of it as a Turing machine that can do useful work. He has pushed the edge of computation per watt for years. That being said, I've heard him talk about this chips for years and it is great to see it finally see the light…

I have done my Master's work with the XCore (xmos.com), which is a direct descendant of the Transputer. It's programmed in an C-with-CSP-constructs called XC. I found it very easy to write XC correctly. I think that the CSP/transputer idea is really the best way for most parallel programming to happen. MPI and pthreads allow more flexibility, but in most (say, 80%) of cases, that's not needed for your application.

I believe the Go model is based on CSP.

A cursory look at Go reminded me of some time I spent writing OCCAM code.

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#99

Post by [deleted] »

barrkel wrote: post #80
derleth wrote: post #62

Earlier quoted context omitted.

OTOH, LLVM is, if anything, a register machine, so as to better map to the register machines we're implementing in hardware right now.

In practice, the difference between LLVM and a stack machine like CLR or JVM is quite small. LLVM SSA, modulo phi nodes, encodes expressions as DAGs in a completely straightforward sense: every operation names its arguments, and those names serve as unique references to a sub-DAG, since they cannot be reassigned. So given the final operation, you can follow the arguments recursively all the way through, completely tr…

[deleted]

Re: Forth Inventor Chuck Moore's $20 144 core CPU now in full production

#100

Post by aidenn0 »

derleth wrote: post #95
aidenn0 wrote: post #90

Earlier quoted context omitted.

ACtually LLVM isn't a virtual machine, it's a compiler intermediate representation.

And when JVM bytecodes are compiled to machine code by the hotspot optimizer, what is the JVM?

JVM bytecode is runnable on the JVM. LLVM bytecode is runnable on what?
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