101–110 of 152 posts
Earlier quoted context omitted.
What logic family did you use? Standard 74-series TTL chips that existed in 1975 are unlikely to work at 166Mhz, their propagation delay was around 20 ns.
You may be right. Somehow 6 ns stuck in my memory, while internet lookup said the 7400 series was 10 ns. I just recall you had to slow down everything considerably to make it human-viewable.
In the year 1974, Practical Wireless, a UK magazine, published a design for a pong game that connects to a television, called PW Tele Tennis. It uses sixty four NAND gates, twelve NE555 timers, two dozen diodes and some analog parts. It's about the most basic version of the game. They later published a sound effects board and an on-screen scoring board that uses a couple of dozen more chips. http://searle.x10host.com…
Of course, in the mid 80's that was a pedagogical tool to lead us toward register machines and von Neumann architectures, but there were still some old-skool EE hackers around who built things like guidance systems for the Navy which were hybrid analogue/digital "computers" totally without CPUs or code. Today we have FPGAs and high level tools for building ASIC, but cheap microprocessors effectively swept aside an entire approach.
Maybe we missed something. Many small and well constrained problems in IoT type applications might better be served by hard-configured solutions. They would use less power, be immune to malicious network hacking, not need 'firmware' updates,
In the year 1974, Practical Wireless, a UK magazine, published a design for a pong game that connects to a television, called PW Tele Tennis. It uses sixty four NAND gates, twelve NE555 timers, two dozen diodes and some analog parts. It's about the most basic version of the game. They later published a sound effects board and an on-screen scoring board that uses a couple of dozen more chips. http://searle.x10host.com…
The implications of Karnaugh maps and state machine reduction, which we did in "Digital Logic" when I was a student, were that you could take any problem, express it as a set of states and transforms, and boil that down to an optimal netlist of discrete logic gates. Of course, in the mid 80's that was a pedagogical tool to lead us toward register machines and von Neumann architectures, but there were still some old-s…
In the year 1974, Practical Wireless, a UK magazine, published a design for a pong game that connects to a television, called PW Tele Tennis. It uses sixty four NAND gates, twelve NE555 timers, two dozen diodes and some analog parts. It's about the most basic version of the game. They later published a sound effects board and an on-screen scoring board that uses a couple of dozen more chips. http://searle.x10host.com…
The implications of Karnaugh maps and state machine reduction, which we did in "Digital Logic" when I was a student, were that you could take any problem, express it as a set of states and transforms, and boil that down to an optimal netlist of discrete logic gates. Of course, in the mid 80's that was a pedagogical tool to lead us toward register machines and von Neumann architectures, but there were still some old-s…
Boards full of TTL are a fascinating engineering exercise, but there aren't many applications where they're a better solution.
It's also tempting to cheat and solve some of the sub-problems with monostables and analog timers. As soon as you do that you're introducing potential issues caused by temperature drift, component tolerances, and component ageing.
A fully clocked solution is always more reliable, but often that means a higher component count and cost.
FPGAs have real applications, but they're still harder to develop than code.
When I was a student one of the tutors said "We'll all be doing this in software soon" - and he was right.
Earlier quoted context omitted.
The implications of Karnaugh maps and state machine reduction, which we did in "Digital Logic" when I was a student, were that you could take any problem, express it as a set of states and transforms, and boil that down to an optimal netlist of discrete logic gates. Of course, in the mid 80's that was a pedagogical tool to lead us toward register machines and von Neumann architectures, but there were still some old-s…
The problems are power consumption, speed, cost, size, development time, and the difficulty of updates and bug fixes. A modern embedded processor handily solves all of those. Boards full of TTL are a fascinating engineering exercise, but there aren't many applications where they're a better solution. It's also tempting to cheat and solve some of the sub-problems with monostables and analog timers. As soon as you do t…
We as EE engineers learned to test our creations. We are however slowly pushed to a SW process world where there are modules and integration tests and at the end, testing is just pingponged between EE and System and nobody do the testing.
Earlier quoted context omitted.
The literal clock speed of CPUs has been stalling, but CPU performance is and has been on a massive increasing trend effectively ever since AMD released the first Ryzen CPUs. Recent product announcements from Intel and AMD show no sign of slowing down. Sure it's not the 'double performance in 1-2 generations' of the olden days, but it's definitely not stalled either.
The Ryzen 7 2700X chip I bought back in 2018 is still fairly close to the latest Ryzen 9 chips in terms of single-core performance on benchmarks (within 10% IIRC). The Ryzen 7 is an 8-core (16 thread) CPU, and now you can get 12 or 16 core Ryzen 9's, but most workloads don't take proper advantage of even an 8-core machine.
Earlier quoted context omitted.
The implications of Karnaugh maps and state machine reduction, which we did in "Digital Logic" when I was a student, were that you could take any problem, express it as a set of states and transforms, and boil that down to an optimal netlist of discrete logic gates. Of course, in the mid 80's that was a pedagogical tool to lead us toward register machines and von Neumann architectures, but there were still some old-s…
The problems are power consumption, speed, cost, size, development time, and the difficulty of updates and bug fixes. A modern embedded processor handily solves all of those. Boards full of TTL are a fascinating engineering exercise, but there aren't many applications where they're a better solution. It's also tempting to cheat and solve some of the sub-problems with monostables and analog timers. As soon as you do t…
That's the only one I don't quite understand. All your other points are definitely great objections.
Are you saying that a clocked system consistently uses less power than a stateful but quiescently 'static' circuit? I can imagine there's a reason, but it goes counter to my experience that the faster you clock a microprocessor the more power it consumes; therefore at zero clock rate a purely data-driven system should consume the least power. What am I missing?
When I was a kid, I remember being at my local arcade and seeing them open up Monaco GP to service it. My mind was completely blown by the hundreds and hundreds of wires and I couldn't fathom how anyone could make sense of it. I believe this is another game that doesn't have code or a CPU, but uses discrete logic circuitry instead. ...Which, I think, is why it's not emulated in MAME.
Earlier quoted context omitted.
The implications of Karnaugh maps and state machine reduction, which we did in "Digital Logic" when I was a student, were that you could take any problem, express it as a set of states and transforms, and boil that down to an optimal netlist of discrete logic gates. Of course, in the mid 80's that was a pedagogical tool to lead us toward register machines and von Neumann architectures, but there were still some old-s…
The problems are power consumption, speed, cost, size, development time, and the difficulty of updates and bug fixes. A modern embedded processor handily solves all of those. Boards full of TTL are a fascinating engineering exercise, but there aren't many applications where they're a better solution. It's also tempting to cheat and solve some of the sub-problems with monostables and analog timers. As soon as you do t…
Earlier quoted context omitted.
The Ryzen 7 2700X chip I bought back in 2018 is still fairly close to the latest Ryzen 9 chips in terms of single-core performance on benchmarks (within 10% IIRC). The Ryzen 7 is an 8-core (16 thread) CPU, and now you can get 12 or 16 core Ryzen 9's, but most workloads don't take proper advantage of even an 8-core machine.
Quick online research shows a 30%-40% single core improvement from the 2700X to the 5700X, and a 40% to 50% (single core) improvement to the 5900X. Maybe you have a specific weird workload that isn't improved much, but performance improvement for the average workload is much better than 10%.