> Thus reasonable to speculate that a process node advancement would at least put Intel's chip on par with M1 on both perf and efficiency
We'll see, but I highly doubt that Intel-at-equivalent-of-TSMC-5nm will be performance/watt competitive with the M1. Apple gets that power efficiency via an extremely wide-and-deep design that intentionally trades off a surprisingly low max clock ceiling (3.2GHz) for power efficiency while maintaining an absurdly high IPC (something like 75% higher than Intel's IPC at only one process node smaller) that makes it much more competitive on performance than conventional industry wisdom ever expected (there is and has been for years a strong belief that a design as wide as Apple's would be grossly inefficient because you could not possibly extract enough instruction level parallelism to keep so many decoders/execution units saturated -- hence we've spent over a decade with 4-5 wide frontends being the "practical maximum" that allows them to still target ~5GHz turbo speeds, which was believed to be basically the best/only path to high performance within what was believed to be the limit of "achievable" IPC. The M1 blows these fundamental assumptions out of the water).
So Intel makes conventional design decisions that make up the performance of their lower clock-for-clock IPC by turboing well north of 5GHz, at the cost of consuming something like 7x the max power of the M1. A single node shrink isn't going to buy them a 75% increase in IPC (their last 4 or 5 node shrinks combined haven't bought them that much IPC increase), so Intel@equivalent-of-TSMC-5nm still going to have to burn power like crazy to stay competitive on performance, and that's going to cost them efficiency that the node shrink just can't paper over.
It will lead in absolute perf, but its not going to be nearly as efficient.