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Intel's New Chimera: Alder Lake

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Re: Intel's New Chimera: Alder Lake

#181

Post by sudosysgen »

paulmd wrote: post #69
delusional wrote: post #46

Earlier quoted context omitted.

It's worth making it explicit that many home computing tasks are highly parrallelizable because the work is actually completely separate programs. If you watch a video while writing a document in word, that's trivially parrallelizable.

It’s also not very intensive, especially since video decode usually runs on the GPU. (Or it should - browsers are not always very good about this but the tools are there, they just don’t want to pay licensing fees to use them.) I always cringe a bit when people insist they need 6 cores “so they can have discord and Spotify open while they game”. People don’t generally have a very good intuitive sense of just how litt…

Games can trivially use 3-4 cores, so a 6 core CPU for gaming+Discord+Spotify is justified.

Re: Intel's New Chimera: Alder Lake

#182

Post by epsilon_greedy »

Traster wrote: post #80

You get a bunch of smart hardware guys into a room, they design this funky exotic architecture. Then the software goes "Allocate these threads to whatever is idle" and suddenly you've completely lost any possible advantage and are thrashing around with no idea what you're doing. The big-little architecture from Apple was accompanied by software that basically handles that for you. From what I heard there were similar…

As part of alder lake intel includes thread director which handles thread dispatch via hardware and software, I believe. The main downside as far as I know is you have to run a very recent kernel to have access to this.

Re: Intel's New Chimera: Alder Lake

#183

Post by mister_tee »

arinlen wrote: post #154
delusional wrote: post #46

Earlier quoted context omitted.

It's worth making it explicit that many home computing tasks are highly parrallelizable because the work is actually completely separate programs. If you watch a video while writing a document in word, that's trivially parrallelizable.

> It's worth making it explicit that many home computing tasks are highly parrallelizable because the work is actually completely separate programs. That's a great point. At any point in time there are already dozens of processes running, of which only a fraction are tied to a GUI. Even GUI apps are currently resorting to launching multiple processes. For example, Firefox announced last year their new site isolation…

possibly chromium-based browsers have had site isolation for about 4 years as well

https://security.googleblog.com/2018/07/mitigating-spectre-w...

Re: Intel's New Chimera: Alder Lake

#184

Post by windowsrookie »

willis936 wrote: post #105
paulmd wrote: post #69

Earlier quoted context omitted.

It’s also not very intensive, especially since video decode usually runs on the GPU. (Or it should - browsers are not always very good about this but the tools are there, they just don’t want to pay licensing fees to use them.) I always cringe a bit when people insist they need 6 cores “so they can have discord and Spotify open while they game”. People don’t generally have a very good intuitive sense of just how litt…

Sure chat apps and video playback are light, but what isn't is browsing the web. Web browsing has become a heavy task. If you tried to install a browser and then use it today on a core 2 duo, you'd have a very bad time. And everyone browses the web, usually quite a bit.

I recently picked up a 2008 17" MacBook Pro. (2.5ghz core 2 Duo).

It browses the web perfectly fine, plays YouTube, and runs VS code, all that the same time. The only website I've notice it struggles on is Google maps, but Google maps has a 2D mode than runs great.

It did actually surprise me how well it runs and now I've been using it as my main machine for a few weeks.

Re: Intel's New Chimera: Alder Lake

#185

Post by pengaru »

zasdffaa wrote: post #34
szastamasta wrote: post #28

Earlier quoted context omitted.

I see nothing particularly hard in utilising 32 cores. When I launch all the services in the project I’m working on my os has plenty work to schedule. Right now I have 3732 threads running on my machine. It’s totally separate question if OS can schedule so many threads effectively on so many cores, and how much coordination overhead there will be. But that’s just something we have to figure out and fix.

I'm interested, what are you doing that can eat all those cores>

It's pretty easy to eat up cores when you're developing graphics rendering algorithms, which can be far more convenient and ergonomic to do on the CPU in a general purpose compiled language, and scaling out via plain old threads.

A CPU with so many general purpose high-perf cores that it manages to look like a GPU in terms of execution units count is a beautiful thing.

Re: Intel's New Chimera: Alder Lake

#186

Post by seunosewa »

helldritch wrote: post #153
hyperbovine wrote: post #137

Earlier quoted context omitted.

I should not like to have to read that document.

That's a fair point, although some people do constantly multitask. I have ADHD and I'm capable of doing work while focussing entirely on two tasks, often I'm looking at one screen where I'm writing code while reading an article on another screen. Sometimes I feel like "reality" is too slow and I've already figured out the code for the unit test (or whatever I'm working on) in my head and I'm impatiently waiting for m…

Your ADHD medication is performance enhancing.

Re: Intel's New Chimera: Alder Lake

#187

Post by adam_arthur »

n7pdx wrote: post #168
adam_arthur wrote: post #22

Earlier quoted context omitted.

AMD beats them because they are a process node ahead. Dunno why every comment implies there's some design gap that leads to M1 or AMD being more powerful or efficient. It's 90% the process node. There is no magic design sauce that makes those chips better. The big/little design change did seem to improve performance quite a bit for Intel, even using the same manufacturing node as before

"Dunno why every comment implies there's some design gap that leads to M1 or AMD being more powerful or efficient." That is because there is a huge design gap. Intel architecture and design teams have always assumed on the inevitability of their own manufacturing superiority and process advantage and thus never had to really consider where to place transistors for the most benefit, or think really hard on better ways…

Intel's chip is more powerful than M1 on an older process node. So where is the design gap?

Re: Intel's New Chimera: Alder Lake

#188

Post by fancyfredbot »

beebeepka wrote: post #48
matthews2 wrote: post #31

Earlier quoted context omitted.

Agner Fog's analysis and guidance is gold to anyone trying to optimise software for a specific microarchitecture.

I see. Yet, this particular entry only contains tiny amounts of well known information. I feel like this product line has been well covered for months now. Oh well.

Was it really "well known" that the complex number multiplication opcodes needed the destination to differ from the source or that the intermediate results were rounded to ensure they were commutative?

Re: Intel's New Chimera: Alder Lake

#189

Post by _zoltan_ »

zasdffaa wrote: post #78
zhdc1 wrote: post #74

Earlier quoted context omitted.

Not the same use case, but we regularly saturate 48 cores doing simple - and heavily parallelized - text analysis and language processing work. So much so that I’m now trying to figure out whether we can somehow cheaply move to a dual Epyc 7742 setup.

Whenever I read stuff like this my inner optimiser starts wondering where the CPU is going and why - massive GC cycles, inefficient regexp stuff, poor algo choice, bad cache locality, etc etc. At the risk of ill manners but i must ask, have you looked at all this because I've got in some cases orders of magnitude speedup by popping the hood and instrumenting.

It's usually cheaper to buy more hardware than to burn engineering hours except at the very low scale (1-2 engineer) and at FAANG scale.

Re: Intel's New Chimera: Alder Lake

#190

Post by kijiki »

kolbusa wrote: post #13
kijiki wrote: post #10

I very much don't understand why Intel didn't disable AVX-512 on the P cores, unless and until the OS writes to a new MSR that means "I understand that the P cores can do AVX-512, while the E cores cannot", and then enable AVX-512 on the P cores. Old OS versions continue to work fine, and newer OS versions can opt into the new world and benefit.

My guess would be that this is because of thread migration. (After reading the TFA: that's what Agner says right there in the 4th paragraph.) (After re-reading the comment: I guess that the OS changes would need to be extensive with little to no benefit: running AVX2 on all cores will likely be faster than running 2 P cores with AVX512. The only thing that is really affected is the code that could use AVX512_FP16, bu…

> I guess that the OS changes would need to be extensive

I don't think that is true. In the simplest case, you could modify the #UD handler to notice when the fault is caused by an AVX512 instruction running on an E-core, and then simply and pin the process to the P-cores, migrate the process, and continue. All existing scheduler functionality.

> The only thing that is really affected is the code that could use AVX512_FP16, but I doubt there's a lot of it outside of Intel.

AVX512 is a lot more than just extending the vector width, and that extended functionality can be very useful for quickly emulating other CPU's vector instruction sets.

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