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Intel's New Chimera: Alder Lake

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Re: Intel's New Chimera: Alder Lake

#13
post #10

I very much don't understand why Intel didn't disable AVX-512 on the P cores, unless and until the OS writes to a new MSR that means "I understand that the P cores can do AVX-512, while the E cores cannot", and then enable AVX-512 on the P cores. Old OS versions continue to work fine, and newer OS versions can opt into the new world and benefit.

My guess would be that this is because of thread migration.

(After reading the TFA: that's what Agner says right there in the 4th paragraph.)

(After re-reading the comment: I guess that the OS changes would need to be extensive with little to no benefit: running AVX2 on all cores will likely be faster than running 2 P cores with AVX512. The only thing that is really affected is the code that could use AVX512_FP16, but I doubt there's a lot of it outside of Intel.)

Re: Intel's New Chimera: Alder Lake

#14
Perhaps the easier option would be DRM software and anything that needs instructions that are only on a specific core type, stick to those cores.

It might reinvolve changes to DRM software but looking at the current compromises, looks like a better deal.

Of course Intel should have thought of this and didn't pick this route. I'd love to see the reasoning though.

Re: Intel's New Chimera: Alder Lake

#15
Other than obvious stuff like differences in features (AVX512 - although I thought that wasn't even officially supported at one point even though they haven't disabled it?) between the P and E cores, how does ARM manage it with big/LITTLE cores? Surely that's similar to a degree (Out of order P cores, in order E cores) to what Intel are attempting?

Are Intel just taking it too far in terms of disparity between the architectures?

Re: Intel's New Chimera: Alder Lake

#16
Personally I don't really see a point in having a hybrid architecture like this unless it'll lead to massively increased core counts, and so far it doesn't look like it does. AMD still beats Intel in both core counts and power efficiency, and they're only using P cores so... what's the point of having E cores?

But maybe that's just because it's a first generation technology for Intel? I hope things improve in the future because I sure would love to have more cores available (currently rocking a 32 core Threadripper) and AMD is sure as hell not interested in actually pushing HEDT forward since they became the top dog. (I have a few grand burning a hole in my pocket waiting for a product they don't want to release.)

Re: Intel's New Chimera: Alder Lake

#18
post #9

I wish there was at least a switch to allow the CPU to report the proper CPUID on each core and ideally, also keep AVX512 enabled. You could have a bios setting writing to an MSR. But I guess some idiot gamer somewhere might still enable this setting without understanding a word of the warning it's accompanied by and Intel wants to avoid that. But I'm hopeful this is a stop-gap solution and we'll just make the p-core…

Such a condescending comment. Why should this "idiot gamer", who might be a child, be expected to know about this stuff?

Why should children be expected to not learn anything the hard way?

Re: Intel's New Chimera: Alder Lake

#19
post #9

I wish there was at least a switch to allow the CPU to report the proper CPUID on each core and ideally, also keep AVX512 enabled. You could have a bios setting writing to an MSR. But I guess some idiot gamer somewhere might still enable this setting without understanding a word of the warning it's accompanied by and Intel wants to avoid that. But I'm hopeful this is a stop-gap solution and we'll just make the p-core…

Such a condescending comment. Why should this "idiot gamer", who might be a child, be expected to know about this stuff?

Yes, an attempt at sarcastically describing Intels train of thought was made. But really, why would a child change random bios settings anyway? You can easily render your system unbootable by changing random things there. Better make knifes illegal before an unsupervised toddler hurts themselves?

Re: Intel's New Chimera: Alder Lake

#20
post #10

I very much don't understand why Intel didn't disable AVX-512 on the P cores, unless and until the OS writes to a new MSR that means "I understand that the P cores can do AVX-512, while the E cores cannot", and then enable AVX-512 on the P cores. Old OS versions continue to work fine, and newer OS versions can opt into the new world and benefit.

They have, haven't they? And officially it was never supported. The article even mentions it: some BIOSs had the ability to override it, but it sounds like that's been disabled in the microcode?
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