81–90 of 138 posts
SGX is used by Signal’s server[0] to allow an open source trust-Intel / trust-their-hardware, but no one else based private contact discovery. [0] https://signal.org/blog/private-contact-discovery/
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Even if you dont believe in sgx, the nsa would still have to be in signal's servers somehow, in which case you are probably screwed anyways
Edward Snowden is a public supporter and user of Signal. He's my canary in the coal mine. The moment the US three letter agencies get access to the data on Signal's servers, Snowden's dead. I feel comfortable in the resilience of their architecture as long as he's alive.
Earlier quoted context omitted.
Edward Snowden is a public supporter and user of Signal. He's my canary in the coal mine. The moment the US three letter agencies get access to the data on Signal's servers, Snowden's dead. I feel comfortable in the resilience of their architecture as long as he's alive.
Isn't Snowden alive because the US decided not to kill him? Doesn't sound like killing him is that hard
His only danger at this point is jail.
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MPX sure, that doesn't prevent bringing a new one, otherwise in a couple of years Intel/AMD will be the only ones left standing without hardware memory tagging support.
I mean, having played with MPX for use in a JIT, it was slower than just manually bounds checking.
Earlier quoted context omitted.
Even if you dont believe in sgx, the nsa would still have to be in signal's servers somehow, in which case you are probably screwed anyways
Edward Snowden is a public supporter and user of Signal. He's my canary in the coal mine. The moment the US three letter agencies get access to the data on Signal's servers, Snowden's dead. I feel comfortable in the resilience of their architecture as long as he's alive.
Also the note at the bottom of that page: that they are doing away with AVX-512. A bit sad for those who need to squeeze maximum performance out of a CPU. (I gather it lives on in Xeon and Zen 4.)
What will happen when the Gracemont small cores will be replaced at the end of 2023, is not known yet.
It is still possible that the successor of Gracemont will have AVX-512, in which case the Intel processors with "Hybrid Technology" will also have it, at that time.
Taking into account that Zen 4 is expected to have AVX-512, it is unlikely that Intel has not also planned for Meteor Lake (2023) to have it. Meteor Lake is supposed to be made using a more dense CMOS process than Alder Lake and Raptor Lake, which should enable Intel to implement AVX-512 in the small cores.
Many moons ago, I wrote a prototype on Azure's 'confidential computing' VMs that demonstrated how a computer could 'prove' to another that it was running certain code using 'attestations.' I thought it was cool as hell, and honestly thought that if such a technology held up you could build many interesting things with it. Potentially, it would have had many use-cases in the DeFi industry, privacy-preserving computati…
It is gone now, but IIRC Microsoft was working on a blockchain for inter-enterprise settlement that ran in the secure enclave. It had extremely high throughput and all of the parties could “trust” that the code running was the same, so they were all following the same rules. Neat concept, they killed it before ever sharing source code.
Doesn't that trust fall apart when the SGX has known hacks?
eg bad actors can do their thing
Earlier quoted context omitted.
Isn't Snowden alive because the US decided not to kill him? Doesn't sound like killing him is that hard
Nobody is coming to kill him. The scenario as a whole makes no sense when you think about it with even the most gentle level of scrutiny. His only danger at this point is jail.
The more interesting thing to me than SGX is that all of TSX-NI is deprecated? Not just HLE, but RTM too? Meaning there'll be no more software transactional memory at all?! Anyone able to shed any light on why they're doing this? Is it just security or is it just not worth it even regardless of that? Is there a chance they'll reintroduce it in some form, perhaps in other processor series?
Not a hardware architect, but my spitballing as a compiler writer: Transactional memory is one of those things that constantly sounds like it's a good idea in theory, but it doesn't live up to those ideas in practice. One of the issues with hardware transactional memory is the challenge of spurious aborts or otherwise running up against hardware limits as to how big transactions can be. Another (as far as I'm aware)…
The bigger problem was actually that in many cases where the optimization could be applied there was always a conflict, usually because of updating some sort of statistical counters. So a lot of attempts to optimize this way would de-opt. It could be fixed by changing the way stats were aggregated to be more tx-friendly but few developers ever did it.
Also the note at the bottom of that page: that they are doing away with AVX-512. A bit sad for those who need to squeeze maximum performance out of a CPU. (I gather it lives on in Xeon and Zen 4.)
Doesn't x86-64v4 require it? This throws upside down the whole x86-64 levels concept. What a mess.
[0]: https://www.phoronix.com/scan.php?page=news_item&px=GCC-11-x...