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Single-chip processors have reached their limits

spectrum.ieee.org

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Re: Single-chip processors have reached their limits

#121

Post by eslaught »

bob1029 wrote: post #67

Despite the limitations apparently present in single chip/CPU systems, they can still provide an insane amount of performance if used properly. There are also many problems that are literally impossible to make faster or more correct than by simply running them on a single thread/processor/core/etc. There always will be forever and ever. This is not a "we lack the innovation" problem. It's an information-theoretic /…

Like the sibling comments have indicated, many apparently sequential computations are actually parallelizable. I'll just add finite automata as another example in this category. On the surface it looks quite sequential (process one input at a time), but there are nice parallel algorithms that you can even implement on a GPU!

So yeah, there's a lot of nonobvious parallelism in the world. Just because something seems sequential doesn't mean it is.

I think the real reason why a lot of software is sequential/inefficient in practice is because we're just not smart enough to figure out how to optimize it (or don't have the proper incentives/it's not a priority). But that's something that's conceivably solvable; it's not limited by laws of physics the way hardware is.

Re: Single-chip processors have reached their limits

#122

Post by ceeplusplus »

paulmd wrote: post #94
AceJohnny2 wrote: post #65

Earlier quoted context omitted.

> But consider also that you can stick chiplets on top of each other vertically. The problem there is heat dissipation. Already the performance constraint on consumer chips like the Apple M1 is how well it can dissipate heat in the product it's placed in (see Macbook Air vs Mac Mini). Stacking the chips just makes it worse.

AMD's 5800X3D and the upcoming generation of AMD/NVIDIA GPUs (both of which are rumored to feature stacked cache dies) are going to be real interesting. So far we haven't ever seen a stacked enthusiast die (MCM doesn't feature any active transistors on the interposer) and it will be interesting to see how the thermals work out. This isn't even stacking compute dies either, stacking memory/cache is the low-hanging fru…

Wide and slow is expensive. Very expensive. That's why Apple can do it and nobody else is doing it (in mobile Qualcomm is _cutting_ cache from Arm reference designs and in servers Graviton and Ampere are also cutting cache). It is cheaper for a given performance level to clock your cores as far as they'll go and cheap out on the width of your core if you know your customers either won't or can't care about power efficiency (because they have no better alternatives).

Re: Single-chip processors have reached their limits

#123

Post by Animats »

Is this a solution to a yield problem? Making physically bigger dies is no problem. Wafers are much larger than the individual dies. If the dies are just being laid out flat, there's no density gain.

Multi-chip modules are nothing new. They've been used mostly when either there was a yield problem, or you wanted two different fab technologies. The latter is seen in some imagers and radars.

Re: Single-chip processors have reached their limits

#124

Post by [deleted] »

nine_k wrote: post #30
Dylan16807 wrote: post #29

Earlier quoted context omitted.

> I'll add that many DRAM chips already do something like this, but ironically enough the re-routing mechanism adds complexity which is itself a source of problems, (be it manufacturing or design, such as broken timing promises) The best-performing solution there is probably software. Tell the OS about bad blocks and keep the hardware simple.

I think this is already implemented both in Linux and in Windows; you can tell the OS which RAM ranges are defective. Doing this from the chip side is not there yet, apparently. I wonder when will this be included in the DRAM feature list, if ever. I suspect that detecting defects from the RAM side is not trivial.

[deleted]

Re: Single-chip processors have reached their limits

#125

Post by jacquesm »

jpmattia wrote: post #114
retrac wrote: post #6

The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…

> Wafer scale integration [1] has come up periodically over the years. Not merely years, but decades. I worked with a wafer-scale group in MIT Lincoln Laboratory back in the late 80s. I'd say there is a reason the technology hasn't taken off in the past 35 years, but who knows, maybe now is the time for wafer scale integration to shine. Incidentally, that group was originally Ken Olsen's group, after he left to go fo…

I think a part of this is that the clock speed increases made most other more expensive solutions not yet commercially viable, but now that 'the end' is in sight a lot of those more expensive solutions are making a come back. You could see the same happening in software to mirror the far more exotic hardware that we use now compared to single core CPUs which for a very long time were the norm.

Re: Single-chip processors have reached their limits

#126

Post by apbytes »

eslaught wrote: post #121
bob1029 wrote: post #67

Despite the limitations apparently present in single chip/CPU systems, they can still provide an insane amount of performance if used properly. There are also many problems that are literally impossible to make faster or more correct than by simply running them on a single thread/processor/core/etc. There always will be forever and ever. This is not a "we lack the innovation" problem. It's an information-theoretic /…

Like the sibling comments have indicated, many apparently sequential computations are actually parallelizable. I'll just add finite automata as another example in this category. On the surface it looks quite sequential (process one input at a time), but there are nice parallel algorithms that you can even implement on a GPU! So yeah, there's a lot of nonobvious parallelism in the world. Just because something seems s…

Wait what‽ Do you have any resources you can point to for parallelism in finite automata?

Re: Single-chip processors have reached their limits

#127

Post by adhesive_wombat »

ksec wrote: post #82

Is spectrum.ieee.org becoming another mainstream ( so to speak ) journalism where everything is dumbed down to basically Newspeak. The article is poorly written, the content is shallow and the headline is click bait.

The IET magazine is the same, it's basically New Scientist but more expensive and you get letters after your name too.

My favourite was the old PPARC Frontiers, was glossy but not breathless. But even then, these things never go into much detail.

Re: Single-chip processors have reached their limits

#128

Post by jacquesm »

wmf wrote: post #45
retrac wrote: post #6

The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…

Calling wafer-scale "no interconnect" is kind of misleading since it's still very difficult to stitch reticles and it has yield challenges.

Indeed, that Zdnet article hints at how they solved that but doesn't provide detail enough to make sense of it.

Re: Single-chip processors have reached their limits

#129

Post by hvidgaard »

tgamblin wrote: post #119
bob1029 wrote: post #67

Despite the limitations apparently present in single chip/CPU systems, they can still provide an insane amount of performance if used properly. There are also many problems that are literally impossible to make faster or more correct than by simply running them on a single thread/processor/core/etc. There always will be forever and ever. This is not a "we lack the innovation" problem. It's an information-theoretic /…

All of this is true, but I’ll just be nitpicky to make a point: > Does a future event's processing circumstances maybe depend on all events received up until now? In a parallel prefix sum, the final sum does depend on all prior inputs, but a good parallel implementation runs in O(log(n)) time. It is, of course, not a total ordering problem, but that’s not obvious at first glance — I’ve always thought it was a beautif…

It's a very simple example and knowing that addition is commutative, it's obvious that there is no ordering.

Re: Single-chip processors have reached their limits

#130

Post by CamouflagedKiwi »

nine_k wrote: post #30
Dylan16807 wrote: post #29

Earlier quoted context omitted.

> I'll add that many DRAM chips already do something like this, but ironically enough the re-routing mechanism adds complexity which is itself a source of problems, (be it manufacturing or design, such as broken timing promises) The best-performing solution there is probably software. Tell the OS about bad blocks and keep the hardware simple.

I think this is already implemented both in Linux and in Windows; you can tell the OS which RAM ranges are defective. Doing this from the chip side is not there yet, apparently. I wonder when will this be included in the DRAM feature list, if ever. I suspect that detecting defects from the RAM side is not trivial.

Yep, my last PC developed a defect in one of the RAM modules. Finding it using memtest86 was trivial; easier than figuring out exactly how to tell Windows what to do about it...

Of course it did take a little bit of a hunch to go from "the game I'm playing crashes at this point" to "maybe my RAM is defective". I suppose ECC would help spot this.

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