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Single-chip processors have reached their limits

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Re: Single-chip processors have reached their limits

#21

Post by mrtksn »

2OEH8eoCRo0 wrote: post #16
Veliladon wrote: post #13

The M1 Ultra is fabricated as a single chip. The 12900K is fabricated as a single chip and is still a quarter the size of the M1 Ultra. Ryzen 3 puts 8 cores on a CCX instead of four because DDR memory controllers don't have infinite memory bandwidth (contrary to AMD's wishful nomenclature) and make shitty interconnects between banks of L3. Chiplets are valid strategies that are going to be used in the future but ther…

> The M1 Ultra is fabricated as a single chip. I'm curious how much the M1 Ultra costs. It's such a massive single piece of glass I'd guess it's $1,200+. If that's the case it doesn't make sense to compare the M1 Ultra to $500 CPUs from Intel and AMD.

Wouldn't the price be primarily based on capital investment and not so much on the unit itself? After all, it's essentially a print out on a crystal using reeeeeally expensive printers. AFAIK Apple's relationship with TSMC is more than a customer relationship.

Re: Single-chip processors have reached their limits

#22

Post by nynx »

tragictrash wrote: post #19
nynx wrote: post #8

Earlier quoted context omitted.

There are some new chip manufacturing technique coming down the pipeline, which will lead to prices dropping and likely "wafer-scale" will get to the mainstream.

Could you elaborate? Would love to know more.

Unfortunately, I cannot.

Re: Single-chip processors have reached their limits

#23

Post by candiddevmike »

AceJohnny2 wrote: post #14
retrac wrote: post #6

The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…

To clarify and contextualize a bit what you're saying: The one big obstacle in creating larger chips is defects. There's just a statistical chance of there being a defect on any given surface area of the wafer, defect which generally breaks the chip that occupies that area of the wafer. So historically, the approach was to make more smaller chips and trash those chips on the wafer affected by defects. Then came the "…

Wikipedia link on microlithography if you want a rabbit hole about wafer making:

https://wikipedia.org/wiki/Microlithography

Being able to print something in nanometers is an overlooked technical achievement for human manufacturing.

Re: Single-chip processors have reached their limits

#24

Post by monocasa »

WithinReason wrote: post #17
monocasa wrote: post #9

Earlier quoted context omitted.

Yeah, in the very general case, chip errors are a function of die area. Cutting a die into four pieces so that when an error occurs in manufacturing, you only throw out a quarter of the die area is becoming the right model for a lot of designs. Like all things chips, it's way more complicated than that, fractally, as you start digging in. Like AMD started down this road initially because of their contractual agreemen…

Their GPUs are likely to be multichip for the first time too with NAVI 31 (while Nvidia's next gen will still be single chip and likely fall behind AMD). It also seems like that the cache will be 6nm while the logic will be 5nm and bonded together with some new TSMC technology. At least that can be inferred from some leaks: https://www.tweaktown.com/news/84418/amd-rdna-3-gpu-engineer...

There's a few ways to interpret that. Another interpretation could be that they are simply taping out Navi32 on two nodes, perhaps for AMD to better utilize the 5nm slots they have access to. Perhaps when Nvidia is on Samsung 10nm+++, then the large consumer AMD GPUs get a node advantage already being at TSMC 7nm+++, and so they're only using 5nm slots for places like integrated GPUs and data center parts that care about perf/watt.

But your interpretation is equally valid with the information we have AFAICT.

Re: Single-chip processors have reached their limits

#25

Post by kwhitefoot »

retrac wrote: post #6

The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…

Nothing new under the sun. Ivor Catt was proposing wafer scale computing in the '70s. Large numbers of processors with the ability to route around defective units.

https://www.ivorcatt.org/icrns86jun_0004.htm

Re: Single-chip processors have reached their limits

#26

Post by throwaway4good »

"Single-Chip Processors Have Reached Their Limits

Announcements from XYZ and ABC prove that chiplets are the future, but interconnects remain a battleground"

This could easily have been written 10 years ago, and I bet someone will write it in 10 years again.

We need these really big chips with their big powerful cores because the nature the computing we do only changes very slowly towards being distributed and parallelizable and thus able to use a massive number of smaller but far more efficient cores.

Re: Single-chip processors have reached their limits

#27

Post by Dylan16807 »

throwaway4good wrote: post #26

"Single-Chip Processors Have Reached Their Limits Announcements from XYZ and ABC prove that chiplets are the future, but interconnects remain a battleground" This could easily have been written 10 years ago, and I bet someone will write it in 10 years again. We need these really big chips with their big powerful cores because the nature the computing we do only changes very slowly towards being distributed and parall…

You're implying you can't put big powerful cores on chiplets but that's not true at all.

Re: Single-chip processors have reached their limits

#28

Post by ceeplusplus »

WithinReason wrote: post #17
monocasa wrote: post #9

Earlier quoted context omitted.

Yeah, in the very general case, chip errors are a function of die area. Cutting a die into four pieces so that when an error occurs in manufacturing, you only throw out a quarter of the die area is becoming the right model for a lot of designs. Like all things chips, it's way more complicated than that, fractally, as you start digging in. Like AMD started down this road initially because of their contractual agreemen…

Their GPUs are likely to be multichip for the first time too with NAVI 31 (while Nvidia's next gen will still be single chip and likely fall behind AMD). It also seems like that the cache will be 6nm while the logic will be 5nm and bonded together with some new TSMC technology. At least that can be inferred from some leaks: https://www.tweaktown.com/news/84418/amd-rdna-3-gpu-engineer...

I've yet to see any sort of research out of AMD on MCM mitigations for things like cache coherency and NUMA. Nvidia on the other hand has published papers as far back as 2017 on the subject. On top of that even the M1 Ultra has some rough scaling spots in certain workloads and Apple is by far ahead of everyone else on the chiplet curve (if you don't believe me, try testing lock-free atomic load/store latency across CCX's in Zen3).

Also AMD claimed the MI250X is "multichip" but it presents itself as 2 GPUs to the OS and the interconnect is worse than NVLink.

Re: Single-chip processors have reached their limits

#29

Post by Dylan16807 »

AceJohnny2 wrote: post #15
AceJohnny2 wrote: post #14

Earlier quoted context omitted.

To clarify and contextualize a bit what you're saying: The one big obstacle in creating larger chips is defects. There's just a statistical chance of there being a defect on any given surface area of the wafer, defect which generally breaks the chip that occupies that area of the wafer. So historically, the approach was to make more smaller chips and trash those chips on the wafer affected by defects. Then came the "…

I'll add that many DRAM chips already do something like this, but ironically enough the re-routing mechanism adds complexity which is itself a source of problems , (be it manufacturing or design, such as broken timing promises) Also, NAND Flash storage (SSD) is designed around the very concept of re-routing around bad blocks, because the very technology means they have a wear-life.

> I'll add that many DRAM chips already do something like this, but ironically enough the re-routing mechanism adds complexity which is itself a source of problems, (be it manufacturing or design, such as broken timing promises)

The best-performing solution there is probably software. Tell the OS about bad blocks and keep the hardware simple.

Re: Single-chip processors have reached their limits

#30

Post by nine_k »

Dylan16807 wrote: post #29
AceJohnny2 wrote: post #15

Earlier quoted context omitted.

I'll add that many DRAM chips already do something like this, but ironically enough the re-routing mechanism adds complexity which is itself a source of problems , (be it manufacturing or design, such as broken timing promises) Also, NAND Flash storage (SSD) is designed around the very concept of re-routing around bad blocks, because the very technology means they have a wear-life.

> I'll add that many DRAM chips already do something like this, but ironically enough the re-routing mechanism adds complexity which is itself a source of problems, (be it manufacturing or design, such as broken timing promises) The best-performing solution there is probably software. Tell the OS about bad blocks and keep the hardware simple.

I think this is already implemented both in Linux and in Windows; you can tell the OS which RAM ranges are defective.

Doing this from the chip side is not there yet, apparently. I wonder when will this be included in the DRAM feature list, if ever. I suspect that detecting defects from the RAM side is not trivial.

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