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Single-chip processors have reached their limits

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Re: Single-chip processors have reached their limits

#11

Post by aeturnum »

tempnow987 wrote: post #7

"Reached their limits" - I feel like I've heard this many many times before. Not that I doubt it, but just I've also been impressed with the ingenuity that folks come up with in this space.

I read articles like this as saying "reached their limits [as we currently understand them]." Sometimes we learn we were mistaken and more is possible but it's not reliable and, crucially, when it happens it happens in unexpected ways. The process of talking about when (and why) techniques have hit their useful limits is often key to unearthing the next step.

Re: Single-chip processors have reached their limits

#12

Post by ranger207 »

RcouF1uZ4gsC wrote: post #10

> UCIe is a start, but the standard’s future remains to be seen. “The founding members of initial UCIe promoters represent an impressive list of contributors across a broad range of technology design and manufacturing areas, including the HPC ecosystem,” said Nossokoff, “but a number of major organizations have not as yet joined, including Apple, AWS, Broadcom, IBM, NVIDIA, other silicon foundries, and memory vendors…

Looks like a lot of people who actually build chips are in the organization

https://www.uciexpress.org/membership

Re: Single-chip processors have reached their limits

#13

Post by Veliladon »

The M1 Ultra is fabricated as a single chip. The 12900K is fabricated as a single chip and is still a quarter the size of the M1 Ultra. Ryzen 3 puts 8 cores on a CCX instead of four because DDR memory controllers don't have infinite memory bandwidth (contrary to AMD's wishful nomenclature) and make shitty interconnects between banks of L3.

Chiplets are valid strategies that are going to be used in the future but there are still more tricks that CPU makers have up their sleeves that they need to use out of necessity. They're nowhere near their limits.

Re: Single-chip processors have reached their limits

#14

Post by AceJohnny2 »

retrac wrote: post #6

The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…

To clarify and contextualize a bit what you're saying:

The one big obstacle in creating larger chips is defects. There's just a statistical chance of there being a defect on any given surface area of the wafer, defect which generally breaks the chip that occupies that area of the wafer.

So historically, the approach was to make more smaller chips and trash those chips on the wafer affected by defects. Then came the "chiplet" approach where they can assemble those functional chips into a larger meta-chip (like the Apple M1 Ultra).

But as you're saying, changes in the way chips are designed can make them resilient to defects, so you no longer need to trash that chip on your wafer that's affected by such a defect, and can thus design a larger chip without fear of defects.

(Of course such an approach requires a level of redundancy in the design, so there's a tradeoff)

Re: Single-chip processors have reached their limits

#15

Post by AceJohnny2 »

AceJohnny2 wrote: post #14
retrac wrote: post #6

The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…

To clarify and contextualize a bit what you're saying: The one big obstacle in creating larger chips is defects. There's just a statistical chance of there being a defect on any given surface area of the wafer, defect which generally breaks the chip that occupies that area of the wafer. So historically, the approach was to make more smaller chips and trash those chips on the wafer affected by defects. Then came the "…

I'll add that many DRAM chips already do something like this, but ironically enough the re-routing mechanism adds complexity which is itself a source of problems, (be it manufacturing or design, such as broken timing promises)

Also, NAND Flash storage (SSD) is designed around the very concept of re-routing around bad blocks, because the very technology means they have a wear-life.

Re: Single-chip processors have reached their limits

#16

Post by 2OEH8eoCRo0 »

Veliladon wrote: post #13

The M1 Ultra is fabricated as a single chip. The 12900K is fabricated as a single chip and is still a quarter the size of the M1 Ultra. Ryzen 3 puts 8 cores on a CCX instead of four because DDR memory controllers don't have infinite memory bandwidth (contrary to AMD's wishful nomenclature) and make shitty interconnects between banks of L3. Chiplets are valid strategies that are going to be used in the future but ther…

> The M1 Ultra is fabricated as a single chip.

I'm curious how much the M1 Ultra costs. It's such a massive single piece of glass I'd guess it's $1,200+. If that's the case it doesn't make sense to compare the M1 Ultra to $500 CPUs from Intel and AMD.

Re: Single-chip processors have reached their limits

#17

Post by WithinReason »

monocasa wrote: post #9
gnarbarian wrote: post #3

Are we moving this way because bigger chips with many cores have worse yields? so the answer is to make lots of little chips and fuse then together?

Yeah, in the very general case, chip errors are a function of die area. Cutting a die into four pieces so that when an error occurs in manufacturing, you only throw out a quarter of the die area is becoming the right model for a lot of designs. Like all things chips, it's way more complicated than that, fractally, as you start digging in. Like AMD started down this road initially because of their contractual agreemen…

Their GPUs are likely to be multichip for the first time too with NAVI 31 (while Nvidia's next gen will still be single chip and likely fall behind AMD). It also seems like that the cache will be 6nm while the logic will be 5nm and bonded together with some new TSMC technology. At least that can be inferred from some leaks:

https://www.tweaktown.com/news/84418/amd-rdna-3-gpu-engineer...

Re: Single-chip processors have reached their limits

#19

Post by tragictrash »

nynx wrote: post #8
retrac wrote: post #6

The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…

There are some new chip manufacturing technique coming down the pipeline, which will lead to prices dropping and likely "wafer-scale" will get to the mainstream.

Could you elaborate? Would love to know more.

Re: Single-chip processors have reached their limits

#20

Post by refulgentis »

I'm embarrassed to admit I still don't quite understand what a chiplet is, would be very grateful for your input here.

If a thread can run on multiple chiplets then this is awesome and seems like a solution.

If one thread == one chiplet, then*:

- a chiplet is equivalent to a core, except with speedier connections to other cores?

- this isn't a solution, we're 15 years into cores and single-threaded performance is still king. If separating work into separate threads was a solution, cores would work more or less just fine.**

* put "in my totally uneducated opinion, it seems like..." before each of these, internet doesn't communicate tone well and I'm definitely not trying to pass judgement here, I don't know what I'm talking about!

** generally, for consumer hardware and use cases, i.e. "I am buying a new laptop and I want it to go brrrr", all sorts of caveats there of course

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