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Verilog Is Weird

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Re: Verilog Is Weird

#81

Post by sguav »

anyfoo wrote: post #6

Oh boy, this is a sore subject for me. It's pretty obvious that Verilog and VHDL, modeled after C and Ada respectively, both imperative languages, follow a drastically mismatched paradigm for hardware design, where circuits are combined and "everything happens in parallel". It becomes even more obvious when you have tried a functional alternative, for example Clash (which is essentially a Haskell subset that compiles…

Any recommended resources to get up to a sufficient comprehension of functional programming for an EE who didn't get to study functional programming?

Re: Verilog Is Weird

#82

Post by magicalhippo »

magicalhippo wrote: post #75
rowanG077 wrote: post #74

Earlier quoted context omitted.

It does have identical return values for identical arguments. That doesn't mean the function can't have internal state. Maybe this is more clear in pseudo code: withInternalState(x): buf = Int[100000] buf.fill(x) return buf.sum() The function is pure yet it uses a very large buffer as internal state. That is the same as a circuit that has a internal state(== memories). Could you give a description of a circuit that i…

What I was thinking of was more like a linear shift feedback register. It has zero inputs and outputs random bits, thanks to its non-trivial internal state. Or as we were saying, a register. Could for example be a function which takes a read/write flag and a value, writes the value to the internal state if write flag is set, and returns the internal value. edit: In my softcore I have a function to read/write register…

So your point is you can have temporary variables in pure functions. That's fine.

However how do you implement registers? Do you have to pass around the "register file"? And if so, how does that work?

Like, how would a parallel-to-serial shift register look like? Ie an asynchronous latch updates the internal shift register and an independent clock shifts out the values.

Re: Verilog Is Weird

#83

Post by tsmi »

jstanley wrote: post #32
Taniwha wrote: post #24

I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…

> "always X" just means loop waiting for X I think this is actually not right. There's not any kind of loop that is running, it's triggered by signal edges. That's the fundamental difference between hardware and software that makes hardware difficult for software people. Everything happens simultaneously.

That’s not exactly the right way to think about it. In HDL, you’re writing an algorithm, but the algorithm produces a physical device, not a computation.

It’s like programming a machine to make a watch. At the end you have a watch. Would you say the gears execute in parallel while it measures time?

In some sense it’s right, but in another it’s missing the point.

Re: Verilog Is Weird

#84

Post by Jtsummers »

sguav wrote: post #78
dhdc wrote: post #51

Related: https://insights.sigasi.com/opinion/jan/verilogs-major-flaw/ This is why if you want complete determinism, use VHDL. Unlike verilog, VHDL was developped specifically for describing hardware behavior.

VHDL springs off of ADA, so I wouldn't say it was specifically developed. Anyway, ADA and VHDL are strongly typed, which incidentally works well with critical applications development such as hardware design.

VHDL springs off of Ada (not an acronym, no need to shout or to bring in the Americans with Disabilities Act into a discussion on programming) syntax, but not its semantics (or, its not a continuation of Ada semantics, it does borrow some of them).

PL/SQL (I've never used it) also borrows from Ada's syntax, but not its semantics in any comprehensive sense. This sort of thing was deliberate, similar to how Verilog borrows from C's syntax, or Java apes C's syntax, or JavaScript apes Java's (and C, indirectly). The goal was to extend something familiar with new semantics.

Re: Verilog Is Weird

#85

Post by tsmi »

FPGAhacker wrote: post #57
pjc50 wrote: post #31

Earlier quoted context omitted.

> Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language Yes, and per the other comment this is a huge limitation of them - you don't have Javascript authors saying "you need to work out what you want in this other paradigm and then translate it". You occasionally see people writing C this way though, by working out what they want from th…

The main point of verilog is to simulate digital logic, of which flip flops are just one part. As to the second point, you can do exactly what you said, instantiate a SystemVerilog “AXI bus” interface and connect things to it. With the interface being a single line item in the port map. This comes with its own set of headaches and I’m not always sure it’s worth it.

> The main point of verilog is to simulate digital logic

I disagree. A HDL, which verilog is an instance of, provides a precise description of a digital machine.

Once you have that description, many things can be done with it. For example you can simulate the machine which is to be produced.

The problem is HDL looks like an algorithm, because it is. But it’s not a precise description of a computation, it’s a description of an object.

Most people who I’ve observed program verilog badly do so because they confuse the two. Kinda like confusing giving directions with giving instructions to make a map. Directions and maps are highly related, but they’re not the same thing.

Re: Verilog Is Weird

#86

Post by sguav »

Jtsummers wrote: post #84
sguav wrote: post #78

Earlier quoted context omitted.

VHDL springs off of ADA, so I wouldn't say it was specifically developed. Anyway, ADA and VHDL are strongly typed, which incidentally works well with critical applications development such as hardware design.

VHDL springs off of Ada (not an acronym, no need to shout or to bring in the Americans with Disabilities Act into a discussion on programming) syntax , but not its semantics (or, its not a continuation of Ada semantics, it does borrow some of them). PL/SQL (I've never used it) also borrows from Ada's syntax, but not its semantics in any comprehensive sense. This sort of thing was deliberate, similar to how Verilog bo…

Yes, Ada not ADA, my mistake which ironically Ada's case insensitivity wouldn't have caught :)

Re: Verilog Is Weird

#87

Post by rowanG077 »

magicalhippo wrote: post #75
rowanG077 wrote: post #74

Earlier quoted context omitted.

It does have identical return values for identical arguments. That doesn't mean the function can't have internal state. Maybe this is more clear in pseudo code: withInternalState(x): buf = Int[100000] buf.fill(x) return buf.sum() The function is pure yet it uses a very large buffer as internal state. That is the same as a circuit that has a internal state(== memories). Could you give a description of a circuit that i…

What I was thinking of was more like a linear shift feedback register. It has zero inputs and outputs random bits, thanks to its non-trivial internal state. Or as we were saying, a register. Could for example be a function which takes a read/write flag and a value, writes the value to the internal state if write flag is set, and returns the internal value. edit: In my softcore I have a function to read/write register…

You are seeing a single invocation as running your circuit for a single clock cycle after an arbitrary amount of clock cycles. That's the wrong approach. A single invocation of a circuit takes a stream of values and produces a stream of values. Every invocation start from clock cycle 0.

So yes if your circuit depends on external signals driven by registers living in a different circuit you need to pass those in as inputs. Essentially circuits are composeable just like functions.

A linear feedback shift registers always produces the same stream of values no matter how many times you run it. It's completely pure.

Re: Verilog Is Weird

#89

Post by mathematicaster »

throwaway984393 wrote: post #59

I hate math. Not because "math is hard", but because the language of math is hard. It's unintuitive and minimalist and full of obscure runes and intonations and nothing is ever explained simply. Many of its properties are just conventions the first person came up with and nobody ever decided to consolidate all the quirks into a simpler form. It's unnecessarily hard to learn - especially for those with learning disabi…

You almost got me!

Re: Verilog Is Weird

#90

Post by tsmi »

gswdh wrote: post #54
tsss wrote: post #52

Earlier quoted context omitted.

No, the problem with Verilog is that it tries to be a procedural language like C when digital circuits are inherently parallel and declarative (sequential circuits just being special cases with feedback). VHDL is better, but still pretty bad. Learning digital circuit design on FPGAs would be so much easier if there was a well supported hardware description language that isn't stuck in the 1980s.

It doesn't. Just because it shares some syntax with C does not make it 'want to be procedural'. I think that comes from the programmers bias from first learning a procedural language. I learnt C then Verilog, I am fluent in Verilog. The mindset for designing digital logic is completely different to programming computers, it literally is a completely different skill. The problem is, people think just because they can…

I do totally agree with the comment, and even upvoted it, but in some sense an HDL does 'want to be procedural'. For example:

   Procedure to make brick wall:
   For brick in wheel-barrow do
     To brick, apply mortar, place it, pound it with trowel
(Apologies to all masons. I think you can tell my training is electrical engineering.)

I've thought for some time that the main problem with Verilog is that it looks really close, visually, to C and that gives people the wrong impression.

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