Related: https://insights.sigasi.com/opinion/jan/verilogs-major-flaw/
This is why if you want complete determinism, use VHDL. Unlike verilog, VHDL was developped specifically for describing hardware behavior.
Verilog Is Weird
51–60 of 131 posts
Re: Verilog Is Weird
#52I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…
No, the problem with Verilog is that it tries to be a procedural language like C when digital circuits are inherently parallel and declarative (sequential circuits just being special cases with feedback). VHDL is better, but still pretty bad. Learning digital circuit design on FPGAs would be so much easier if there was a well supported hardware description language that isn't stuck in the 1980s.
Re: Verilog Is Weird
#53I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…
> Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language Yes, and per the other comment this is a huge limitation of them - you don't have Javascript authors saying "you need to work out what you want in this other paradigm and then translate it". You occasionally see people writing C this way though, by working out what they want from th…
> "you need to work out what you want in this other paradigm and then translate it"
Not really. You wouldn't expect good programs from someone who has no idea how a computer works. The language is the knobs and dials. You need to know what the knobs and dials do in the machine.
Re: Verilog Is Weird
#54I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…
No, the problem with Verilog is that it tries to be a procedural language like C when digital circuits are inherently parallel and declarative (sequential circuits just being special cases with feedback). VHDL is better, but still pretty bad. Learning digital circuit design on FPGAs would be so much easier if there was a well supported hardware description language that isn't stuck in the 1980s.
It doesn't. Just because it shares some syntax with C does not make it 'want to be procedural'. I think that comes from the programmers bias from first learning a procedural language.
I learnt C then Verilog, I am fluent in Verilog. The mindset for designing digital logic is completely different to programming computers, it literally is a completely different skill. The problem is, people think just because they can type a (procedural) programming language they can program anything that is programmed with a code which is where peoples initial distaste for Verilog and VHDL comes from. When you learn how to do it, I think designing logic is refreshing compared to writing software, there's so much baggage with software.
Re: Verilog Is Weird
#55Earlier quoted context omitted.
Logged in just to upvote this and largely agree with you. Verilog/VHDL are stuck at the 1980s coding paradigm level, as if the industry grabbed the first working solution for automated hardware developement and has clung on to it. > The problem is, it is hard, if not downright impossible, to get the industry to change. Yes. I don't think it will until either, say, Intel does it by CEO fiat, like the Amazon memo, or a…
> A monad is just a monoid in the category of endofunctors By the way, this (and similar) definitions are fun but not very useful (because nobody thinks in terms of the category of endofunctors).
Yes, that's the joke, it's from http://james-iry.blogspot.com/2009/05/brief-incomplete-and-m... - but the joke is that advanced users of any concept have a tendency to explain it in terms of concepts that the audience also doesn't understand.
Re: Verilog Is Weird
#56Oh boy, this is a sore subject for me. It's pretty obvious that Verilog and VHDL, modeled after C and Ada respectively, both imperative languages, follow a drastically mismatched paradigm for hardware design, where circuits are combined and "everything happens in parallel". It becomes even more obvious when you have tried a functional alternative, for example Clash (which is essentially a Haskell subset that compiles…
Writing performant DSP for an FPGA involves using intrinsics/structures specific to the device. A multiply and accumulate for example. Can you easily take advantage of stuff like that in clash? What about using the existing device dependent IP linraries? I agree verilog/vhdl are fairly dated, and not designed for how we use these devices today. An increasing number of people I talk to are generating their designs from hdl coder or model composer type tools.
Re: Verilog Is Weird
#57I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…
> Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language Yes, and per the other comment this is a huge limitation of them - you don't have Javascript authors saying "you need to work out what you want in this other paradigm and then translate it". You occasionally see people writing C this way though, by working out what they want from th…
The main point of verilog is to simulate digital logic, of which flip flops are just one part.
As to the second point, you can do exactly what you said, instantiate a SystemVerilog “AXI bus” interface and connect things to it. With the interface being a single line item in the port map. This comes with its own set of headaches and I’m not always sure it’s worth it.
Re: Verilog Is Weird
#58Earlier quoted context omitted.
Verilog definitely sucks but I think the problem with new HDLs (Clash, Bluespec, Chisel etc) is they don't necessarily make the hard bits of hardware design easier, they just help with the tedious stuff that whilst annoying ultimately doesn't take up much of your time. For example a good type system definitely makes module interfaces cleaner, saves you having to dig through warnings/lint reports to find stupid errors…
I've tried pretty much every 'NeoHDL' out there, and so far Bluespec was the one that actually made me feel like it's a step in the right direction, instead of more of the same. Its atomic transaction based modelling maps superbly well into hardware clock cycles, and after using it for a while you learn to visualize quite well what shape of RTL will be generated. Plus its standard library provides some really powerfu…
Yes I did quite like bluespec, though after my time using it I drew two conclusions.
1. The extra power I had to build parameterisable/configurable designs didn't help as much as you'd hope as I said in my earlier post. Making something that can deal with a large parameter space still remains hard, the easier things look a lot nicer and are less fiddly to work with but on a practical level you're not gaining much.
2. One of bluespec's big ideas is you write the rules, with conditions and it works out the rest. The problems come when this maps to verilog and you need to start fixing implementation issues. I ended up having to develop good intuition around exactly how the compiler would schedule the rules so I could avoid issues (e.g. combinational loops). It felt like bluespec really pushed you into deep pipelining, rule does one thing result gets flopped another rule will take over next cycle. Fine for some designs but sometimes you've got a whole bunch of stuff you want to get in a single cycle (e.g. within a CPU) and there I felt like the rules construct ultimately just made it harder to build anything.
I do remember discovering some 'hidden' language features. Knowing it all turned into Haskell underneath via term rewriting I tried some syntactic constructs that weren't documented but I felt should work and often found they did! This gave some fairly powerful stuff to play with though never good to rely on undocumented features.
As I said it was over 10 years ago so my memory is hazy, things may have improved since there as has my skill and experience. I should really take another look now the compiler is open.
Re: Verilog Is Weird
#59I hate math. Not because "math is hard", but because the language of math is hard. It's unintuitive and minimalist and full of obscure runes and intonations and nothing is ever explained simply. Many of its properties are just conventions the first person came up with and nobody ever decided to consolidate all the quirks into a simpler form. It's unnecessarily hard to learn - especially for those with learning disabilities.
It turns out there are lots of languages like this. C and Verilog and Assembly, and ... Cantonese, Albanian, Russian, Arabic. Ask people why they're like that and there is always a story, and usually some good reasons (or at least useful qualities). But language is a part of culture, and sadly, culture is incredibly hard to change.
Re: Verilog Is Weird
#60I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…
>> always @(posedge clk)
Is there an option for bothedge clk?