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Verilog Is Weird

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Re: Verilog Is Weird

#41

Post by Koshkin »

pjc50 wrote: post #11
anyfoo wrote: post #6

Oh boy, this is a sore subject for me. It's pretty obvious that Verilog and VHDL, modeled after C and Ada respectively, both imperative languages, follow a drastically mismatched paradigm for hardware design, where circuits are combined and "everything happens in parallel". It becomes even more obvious when you have tried a functional alternative, for example Clash (which is essentially a Haskell subset that compiles…

Logged in just to upvote this and largely agree with you. Verilog/VHDL are stuck at the 1980s coding paradigm level, as if the industry grabbed the first working solution for automated hardware developement and has clung on to it. > The problem is, it is hard, if not downright impossible, to get the industry to change. Yes. I don't think it will until either, say, Intel does it by CEO fiat, like the Amazon memo, or a…

> A monad is just a monoid in the category of endofunctors

By the way, this (and similar) definitions are fun but not very useful (because nobody thinks in terms of the category of endofunctors).

Re: Verilog Is Weird

#42

Post by JoachimS »

anyfoo wrote: post #6

Oh boy, this is a sore subject for me. It's pretty obvious that Verilog and VHDL, modeled after C and Ada respectively, both imperative languages, follow a drastically mismatched paradigm for hardware design, where circuits are combined and "everything happens in parallel". It becomes even more obvious when you have tried a functional alternative, for example Clash (which is essentially a Haskell subset that compiles…

At least for me, OOP was the obvious better model for modelling HW than either imperative and functional based paradigm. Modules, cores in HW have an internal state and defines interfaces. The internal state is updated due both to the internal state itself and changes to inputs.

SystemVerilog fixed several pain points in Verilog, one of the more important the ability to encapsulate, bundle ports and protocol handling (logic and state) in interfaces that can be instantiated in modules. You can still shoot yourself by "progam in Verilog", that is forgetting that you are in fact describing physical and electrical reality, but you can write code with less errors.

Ome thing I see SW people not understand is that the toolchains for ASIC development are much biggers. You have simulators, compilers, linters, floorplanner, signal integrity analyzers, detailed Place & Route, several levels of formal verification tools, test insertion and test automation tools etc etc. All of these tools need to parse one or more source files. And all these tools need to parse the source files in the same way. This, in combination with the possible HUGE cost (money and time to market) of taping out a chip that requires a respin, change of one or or more of the masks in the maskset are big reasons why the industry is very conservative to radical changes in language. The subset of language features that are safe to use (i.e. correctly parsed and usable through the complete toolchain) is often surprisingly small. And to be honest, describing the HW you want is often the least hard part of chip design

Thinking that the chip industry and associated EDA industry simply don't know CS and modern tools, SW paradigms probably means missing what is actually hard when designing chips.

A final note on functional languages - as you state "It's no news that Haskell can be very hard to get into for even experienced software engineers." This is also a possible reason for lack of adoption. You basically reduce the set of potential engineers. And finding good digital, SoC and chip designers is already very hard. After seeing several attempts and cool ideas I'm quite convinced that the subset of engineers groks and likes functional languages and groks and likes electrical engineering, digital and chip design is too small to scale to meet industry needs.

Rant off. I'm accepting that yes I'm probably in the "has no idea what higher order functional programming with advanced type system is on any level" camp.

Re: Verilog Is Weird

#43

Post by meetups323 »

q3k wrote: post #39
gchadwick wrote: post #20

Earlier quoted context omitted.

Verilog definitely sucks but I think the problem with new HDLs (Clash, Bluespec, Chisel etc) is they don't necessarily make the hard bits of hardware design easier, they just help with the tedious stuff that whilst annoying ultimately doesn't take up much of your time. For example a good type system definitely makes module interfaces cleaner, saves you having to dig through warnings/lint reports to find stupid errors…

I've tried pretty much every 'NeoHDL' out there, and so far Bluespec was the one that actually made me feel like it's a step in the right direction, instead of more of the same. Its atomic transaction based modelling maps superbly well into hardware clock cycles, and after using it for a while you learn to visualize quite well what shape of RTL will be generated. Plus its standard library provides some really powerfu…

Agree Bluespec is great. In college we went from 0 to a Bluespec multicore RISC-V processor running Linux on an FPGA in a single undergrad semester, every step along the way felt intuitive.

Re: Verilog Is Weird

#44

Post by JoachimS »

OJFord wrote: post #17
jiggawatts wrote: post #13

Earlier quoted context omitted.

One thing I don't quite understand about using Haskell for circuit design is that at a first glance it also seems like pure functional programming has an impedance mismatch with what the circuitry physically does. (For reference, I've programmed in Haskell extensively before.) For example, much of Haskell directly or indirectly relies on recursion -- but this nearly nonsense when talking about silicon! There's no cal…

That was my reaction. Why not something declarative, like Prolog (bonus: sounds like it could be the advanced version of Verilog) or HCL (Hashicorp Configuration Language, as used for Terraform)? I've been thinking of writing a tool to use the latter for EDA, so you could build libraries of composable reusable blocks, take application note type examples directly rather than re-draw, etc. and (what motivated me initia…

This has been tested several times, and used be a fairly common EDA academic reserach subjest. (As well as other languages like Haskell, SML). I first saw Prolog used for HW design in 1995 or so. A bit newer example is this: https://www.researchgate.net/publication/220760154_A_Prolog-...

One important area is digital systems testing. There stuff like Prolog seems to me a better fit than for actual HW description. For test cases I want to efficiently describe the behaviour, esp inputs, expected outputs and changes to state.

For the design, I'm not only interested in that I get the correct behaviour (functionally correct), but also _how_ I get the behaviour. How much resources are needed, what does the routing look like, how many metal layers does it to route, how much power will it consume, how fast can I clock the design.

Re: Verilog Is Weird

#45

Post by hyperman1 »

I wonder why building circuits doesn't use a language comparable to the nand2tetris course.

For those who haven't seen it: It gives building blocks like NAND, wires, and an abstraction method, allowing to treat a group of wires and building blocks as a new building block. So you wire up a few gates to, say, an adder, then you can use adders in your circuit.

Things like circuit synthesis and timing analysis get trivial. I have the impression digital designers already tend to think in this way.

I don't have much experience,so read the next as a question instead of a suggestion: what's wrong with using this as a basis for a new design language?

Re: Verilog Is Weird

#46

Post by JoachimS »

rocqua wrote: post #25
anyfoo wrote: post #6

Oh boy, this is a sore subject for me. It's pretty obvious that Verilog and VHDL, modeled after C and Ada respectively, both imperative languages, follow a drastically mismatched paradigm for hardware design, where circuits are combined and "everything happens in parallel". It becomes even more obvious when you have tried a functional alternative, for example Clash (which is essentially a Haskell subset that compiles…

> So that basically leaves the intersection of people that are both enthusiastic software engineers with an affection for e.g. Haskell, and also enthusiastic in building hardware. But outside of my own projects, it just leaves me longing for the world that could exist. It seems to me that a shop made exclusively of people with this background would be massively more productive, and quite an attractive place to work f…

The size of that intersection. And the need to at some point interface to the rest of the world, including the EDA world.

Unless you build your own products from system to physical chips in house (have your own fab) sooner or later you will need to interact, exchange source code or netlists in some form. Fabs expect you to use certain (golden) tools before accepting a design for manufacturing.

Re: Verilog Is Weird

#47

Post by rowanG077 »

Koshkin wrote: post #40
rowanG077 wrote: post #21

Earlier quoted context omitted.

Why do you feel there is a mismatch? Any digital circuit can be modeled with a pure function that transforms an input stream of values to an output stream of values. And that is actually precisely what Clash does. Regarding recursion. I believe Clash does support a limited form of recursion. Namely if you prove every recursive call leads to the problem size strictly decreasing. e.g. recursion on a vector of size n mu…

> Why do you feel there is a mismatch? Can this be because in digital circuits state (memory) plays an important role, while its treatment in a (pure) functional language is not straightforward?

It's straightforward to implement memory in a pure function. For example if you say a digital circuit is a function from infinite list of inputs to an infinite list of outputs. You can create a "register" by simply adding a value to the start of the list. For example in Haskell:

delayCircuit xs = 0:xs

take 10 (delayCircuit [1..])

-- [0,1,2,3,4,5,6,7,8,9]

Whether a function is pure doesn't mean it can't have internal state. As another example it's perfectly fine to have a completely pure function that has internal state:

withInternalState a = let go = get >>= \s -> put (s + 1)

                      in fst (runState go a)
What is important for purity is that this internal state doesn't leak outside the function. Which it doesn't for circuits. Outside of things like cosmic rays, heating etc a circuit is completely pure in reality.

Re: Verilog Is Weird

#48

Post by gh02t »

hyperman1 wrote: post #45

I wonder why building circuits doesn't use a language comparable to the nand2tetris course. For those who haven't seen it: It gives building blocks like NAND, wires, and an abstraction method, allowing to treat a group of wires and building blocks as a new building block. So you wire up a few gates to, say, an adder, then you can use adders in your circuit. Things like circuit synthesis and timing analysis get trivia…

I think you mean block based designs where you define blocks as inputs and outputs with the logic inside, and then you can piece together and group blocks with wires possibly in some sort of visual editor or similar format? This is already how Verilog and VHDL work, they are oriented around functional blocks that you wire together to build up more complex units. Often HDL environments ship libraries of pre-made blocks for various functions, many of which are very powerful and might be tuned by the vendor to exploit specific hardware features of your target (the more powerful ones are typically expensive and black box proprietary stuff that you just get input and outputs). They also often provide an actual graphical editor for wiring blocks together, or you can specify connections in a text format.

I'm not really professionally experienced with it, but I understand that a lot of the common work in practice is wiring together these pre-made block libraries from vendors more than writing them from scratch.

Re: Verilog Is Weird

#49

Post by [deleted] »

hyperman1 wrote: post #45

I wonder why building circuits doesn't use a language comparable to the nand2tetris course. For those who haven't seen it: It gives building blocks like NAND, wires, and an abstraction method, allowing to treat a group of wires and building blocks as a new building block. So you wire up a few gates to, say, an adder, then you can use adders in your circuit. Things like circuit synthesis and timing analysis get trivia…

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