Earlier quoted context omitted.
They might have to have the unified memory more dense to get to 1.5 TB max of RAM on the machine (also since this would be originally shared with a GPU). Maybe they could stack the RAM on the SoC or just get the RAM at a lower process node.
The M1 Max/Ultra is already extremely dense design for that approach, it's really almost as dense as you can make it. There's packages stacked on top, and around, etc. I guess you could put more memory on the backside but that's not going to do more than double it, assuming it even has the pinout for that (let's say you could run it in clamshell mode like GDDR, no idea if that's actually possible, but just hypothetic…
You (or the OS or the chip) could page things in and out if the unified memory. Treat unified memory as a MEGA L3 cache.
Depending on how it’s done it may not be transparent if you want the best performance. But would it work?