How “latency numbers everybody should know” decreased from 1990–2020

Post by gameswithgo » Thu, Mar 03, 2022, 10:13 PM UTC

greggsy wrote: post #39

gameswithgo wrote: post #25

An instructive thing here is that a lot of stuff has not improved since ~2004 or so, and working around those things that have not improved (memory latency from ram all the way down to l1 cache really) requires fine control of memory layout and minimizing cache pollution, which is difficult to do with all of our popular garbage collected languages, even harder with languages that don't offer memory layout controls, a…

It’s interesting that L2 cache has basically been steady at 2MB/core since 2004 aswell. It hasn’t changed speed in that time, but is still an order of magnitude faster than memory across that whole timeframe. Does this suggest that the memory speed bottleneck means that there simply hasn’t been a need to increase availability of that faster cache?

Post by raisedbyninjas » Thu, Mar 03, 2022, 10:16 PM UTC

muh_gradle wrote: post #47

ChuckMcM wrote: post #17

Not an intuitive thing but the data is fascinating. A couple of notes of people who are confused by it: 1) The 'ns' next to the box is a graph legend not a data label (normally that would be in a box labeled legend to distinguish it from graph data) 2) The weird box and rectangle thing on the top is a slider, I didn't notice that until I was looking at the code and said "what slider?" 3) The only changes from 2005 to…

I would never have realized the slider functionality until I read this comment.

Post by moonchild » Thu, Mar 03, 2022, 10:20 PM UTC

ianai wrote: post #42

ChuckMcM wrote: post #34

Earlier quoted context omitted.

We probably see things differently. As I understand it, this is exactly the use case for "big/little" microarchitectures. Take a number of big fast cores that are running full bore, and a bunch of little cores that can do things for them when they get tasked. So far they've been symmetric but with chiplets they needn't be.

Yes, for 'computational' loads. I've read though UI/UX benefits the most from fastest response times. I'm talking about the cores which actually draw the GUI the user sees/uses being optimized for the task at the highest possible rate. Then have a pool of cores for the rest of it.

Post by thfuran » Thu, Mar 03, 2022, 10:21 PM UTC

pjc50 wrote: post #49

ChuckMcM wrote: post #17

Not an intuitive thing but the data is fascinating. A couple of notes of people who are confused by it: 1) The 'ns' next to the box is a graph legend not a data label (normally that would be in a box labeled legend to distinguish it from graph data) 2) The weird box and rectangle thing on the top is a slider, I didn't notice that until I was looking at the code and said "what slider?" 3) The only changes from 2005 to…

It also tells us that the speed of light has not increased. (well, speed of signal on a PCB track is roughly 2/3 light and determined by the transmission line geometry and the dielectric constant, but you all knew that)

Post by jll29 » Thu, Mar 03, 2022, 10:23 PM UTC