Earlier quoted context omitted.
> see my response elsewhere, but these aren't unrelated problems: Apple has higher IPC at a lower power-per-core. You can slide around where on the scale x86 falls - maybe you can match perf/watt but then you're getting wiped by a factor of 3 on performance, and you can match on performance but then you're getting wiped by a factor of 6 on perf-watt. You can't do both at once. I'm not sure how you established that. I…
“Intrinsically linked” doesn’t mean anything, if you want to make an argument then make it. I’ve already made mine - Anandtech shows a factor of 6 difference in perf/watt between a 11980HK and a M1 Max at peak performance, and this likely translates into a ~factor of four-ish difference in perf/watt and IPC at iso-power. That’s a performance gap that is unlikely to be closed by a node shrink - there is a large archit…
Yes it does, it's refuting your idea that IPC can be considered without looking at cycle time.
And you're trying to make an argument that does not address the question I asked. As I told you in my first reply.
> Ah, so you are conflating “the amount of transistors spent on x86 decoding” with “the architectural impact that x86 has on performance”.
No. Read the conversation from the start, and read the links with comments from people who have actually worked on Apple, AMD, and Intel cores.