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MiSTer, an open-source FPGA gaming project

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Re: MiSTer, an open-source FPGA gaming project

#41

Post by vardump »

fooblat wrote: post #10

I love my MiSTer build! The usb controllers made for the recent mini systems (NES, SNES, Genesis, etc) make great accessories for the mister. Add a couple of usb arcade sticks and you can really play almost any classic retro games as it was meant to be played. And then there are all the classic computer cores even including the PDP-1!

Yup, same! Can wholeheartedly recommend it for those who want something between emulation and real hardware.

The Amiga core is fun, AGA, 2 MB chip, 384 MB fast. It supports hard disk images, so you can do a hard disk based Workbench installation and load games and demos practically instantly (and safely exit to Workbench) using WHDLoad.

Arcade cores are fun as well. Just like in childhood, but less hungry for quarters. :) Recently played with arcade Gauntlet core a bit for example.

Re: MiSTer, an open-source FPGA gaming project

#42

Post by klodolph »

tediousdemise wrote: post #39
near wrote: post #21

Earlier quoted context omitted.

It is, but these cores are almost exclusively not being done that way. Not yet at least. I hope that they will be, that would be really awesome. I paid $1200 last year for the SNES PPUs to be decapped for this purpose, but it's a truly enormous undertaking to map out those chips and then recreate it in Verilog. You're talking thousands of hours of work per chip. If anyone reading this is able to help with that effort…

By decapped, do you mean delidded? Theoretically it would be possible to automate this with a couple things: - USB electron microscope to image the transistor topology - CV lib to identify connections and generate corresponding Verilog code

“Decapping” is a more intense version of delidding where you use chemical agents or something similarly extreme (laser, plasma, milling) to remove the package (ceramic, plastic).

My understanding is that there are people who do it often enough that it is automated in the way you describe, but you still need someone with a lot of skill to spend serious time on it. Computer vision works wonders but there are errors which must be identified and fixed.

A lot of the chips people care about are can just be done optically, no electron microscope needed.

Re: MiSTer, an open-source FPGA gaming project

#43

Post by djmips »

klodolph wrote: post #40
tediousdemise wrote: post #24

Earlier quoted context omitted.

On FPGAs (depending on the hardware mapping), you get the benefit of lower latency. I consider this to be timing accuracy. Say you have two implementations of an LED controlled by a switch: one which uses an FPGA and one which uses a microcontroller. The uC implementation must continuously poll peripherals connected to its GPIO pins at a set frequency; it must check the state of the switch, and then change the state…

Most game consoles don’t do any of this, though. The gamepad is polled by software. On the NES and SNES, the buttons are connected to a shift register (e.g. 4021). The CPU triggers a latch and then reads out the shift register one bit at a time.

This was given as an example, not for you to straw man about the gamepad.

Re: MiSTer, an open-source FPGA gaming project

#45

Post by tediousdemise »

klodolph wrote: post #42
tediousdemise wrote: post #39

Earlier quoted context omitted.

By decapped, do you mean delidded? Theoretically it would be possible to automate this with a couple things: - USB electron microscope to image the transistor topology - CV lib to identify connections and generate corresponding Verilog code

“Decapping” is a more intense version of delidding where you use chemical agents or something similarly extreme (laser, plasma, milling) to remove the package (ceramic, plastic). My understanding is that there are people who do it often enough that it is automated in the way you describe, but you still need someone with a lot of skill to spend serious time on it. Computer vision works wonders but there are errors whi…

Ah, that’s a good distinction. I’d be pretty scared of damaging the hardware by doing that, but I’m sure there are some really experienced folks out there that would appreciate the hardware donation.

Re: MiSTer, an open-source FPGA gaming project

#46

Post by phendrenad2 »

MiSTer is an amazing phenomenon. The MiSTer itself is just an Intel FPGA devkit, which many believe to be sold at a loss (because it's a training tool and not Intel's main source of FPGA revenue). The amazing thing is the aftermarket for addons. There are many possible combinations of addon boards that add RAM with deterministic latency, USB hubs, cooling fans, cases, retro controller ports, etc. All custom-made for this ecosystem.

Re: MiSTer, an open-source FPGA gaming project

#47

Post by tediousdemise »

near wrote: post #37
cmrdporcupine wrote: post #35

Earlier quoted context omitted.

Lower latency is definitely a thing. With FPGA it's possible to 'chase the beam' like the original hardware, and have much reduced input latency from devices, etc. With an emulator you're going to be fighting the OS and the frameworks you built on top of. Even if you go "bare metal" (like my friend's BMC64 project which runs a C64 emulator like a unikernel on the RPi with no OS) you are still dealing with hardware bu…

That is true. There are however techniques software emulators can use like run-ahead that can get you lower latency than even the original hardware on a PC: https://near.sh/articles/input/run-ahead The caveat is that it doesn't always work, and it makes the power requirements even more unbalanced. Some might also see it as a form of cheating to go below the original game's latency. If you want to match the original g…

Run-ahead seems pretty cool, great technical write up. How would you compare this to the feature called frame-skipping that I often see implemented in software emulators?

Re: MiSTer, an open-source FPGA gaming project

#48

Post by jonny_eh »

tediousdemise wrote: post #15
drewblaisdell wrote: post #11

Earlier quoted context omitted.

I wonder, why is there no DIY Analogue Pocket-style MiSTer project? Is the DE10-Nano too large or inefficient for this?

I’d reckon it’s the same reason that there isn’t much of a custom laptop scene. The open ended nature of stuffing a screen, battery, and input peripherals into a chassis seems an order of magnitude more difficult than just making a headless box to plug into your TV. But with some effort, it would be awesome.

Physical design is also a lot more important. Getting "feel" just right is very hard and expensive, especially when it comes to game controllers.

Re: MiSTer, an open-source FPGA gaming project

#49

Post by someperson »

floatboth wrote: post #12
near wrote: post #6

Earlier quoted context omitted.

It is indeed an amazing project, especially its open source nature. It provides some impressive power savings and latency reductions that are very hard to match with general purpose CPUs. But in most cases, it is emulation, as the lead developer will attest. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Why-FPGA "From my point of view, if the FPGA code is based on the circuitry of real hardware (along with the usu…

Well, yeah, it's not replication if it's not an exact hardware replica, but the word "emulation" has very "software" connotations. I guess let's call it.. recreation? (That word is even in the quote above!)

"FPGA re-implementation" may be a better term

Re: MiSTer, an open-source FPGA gaming project

#50

Post by tinybear1 »

phendrenad2 wrote: post #46

MiSTer is an amazing phenomenon. The MiSTer itself is just an Intel FPGA devkit, which many believe to be sold at a loss (because it's a training tool and not Intel's main source of FPGA revenue). The amazing thing is the aftermarket for addons. There are many possible combinations of addon boards that add RAM with deterministic latency, USB hubs, cooling fans, cases, retro controller ports, etc. All custom-made for…

It is definitely being sold at a loss, the Cyclone V SOC being used costs more than the entire development board.[0] I wonder if Intel will ever take notice due to MiSTer's growing popularity and quit subsidizing the board.

[0] https://www.digikey.com/en/products/detail/intel/5CSEBA6U23I...

Edit: it was erroneous of me to state the board was being sold at a loss, rather I meant that the board was being definitely being subsidized by companies such as Intel and their partners such as Panasonic. My mistake. I also wasn't meaning to convey that the consumer Digikey pricing was the same as the large volume manufacturers such as Terasic. Rather I meant to demonstrate and agree with the OP on the astounding situation that MiSTer currently exists in, owning to the lack of economic viability for someone to produce a low volume commercial FPGA emulation machine for a niche audience without any subsidization.

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