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MiSTer, an open-source FPGA gaming project

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Re: MiSTer, an open-source FPGA gaming project

#31

Post by duskwuff »

drewblaisdell wrote: post #11
tediousdemise wrote: post #8

Earlier quoted context omitted.

The Analogue Pocket[1] is exactly this (albeit proprietary). Out of the box it recreates GB, GBC, and GBA using the Altera Cyclone-V platform. [1] https://www.analogue.co/pocket

I wonder, why is there no DIY Analogue Pocket-style MiSTer project? Is the DE10-Nano too large or inefficient for this?

The DE10-Nano itself is a bit large for a handheld device, and hasn't been optimized for power consumption. (It's designed as a development board, not as a component of a finished product.) There's nothing stopping someone from using the Cyclone-V SoC in a handheld device, though.

Re: MiSTer, an open-source FPGA gaming project

#32

Post by near »

mschuster91 wrote: post #30
near wrote: post #6

Earlier quoted context omitted.

It is indeed an amazing project, especially its open source nature. It provides some impressive power savings and latency reductions that are very hard to match with general purpose CPUs. But in most cases, it is emulation, as the lead developer will attest. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Why-FPGA "From my point of view, if the FPGA code is based on the circuitry of real hardware (along with the usu…

> It's also not a total solution: by taking many more transistors to programmatically simulate just one, it limits the maximum scale and frequency of what it can support. N64/PS1/Saturn has not yet been fully supported and is still theoretical, but likely, to be possible. Going beyond that is not possible at this time. The limiting factor here is the amount of stuff you can throw into a single FPGA, correct? So in th…

There's both a cost and a speed barrier to it. FPGAs are often used to design, simulate, and test modern circuits at sub-realtime speeds. No amount of FPGAs will get you a PS2 emulator at playable speeds right now, let alone a PS3/Switch emulator. PCs can do that today by taking shortcuts such as dynamic recompilation and idle loop skipping.

Re: MiSTer, an open-source FPGA gaming project

#33

Post by duskwuff »

mschuster91 wrote: post #30
near wrote: post #6

Earlier quoted context omitted.

It is indeed an amazing project, especially its open source nature. It provides some impressive power savings and latency reductions that are very hard to match with general purpose CPUs. But in most cases, it is emulation, as the lead developer will attest. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Why-FPGA "From my point of view, if the FPGA code is based on the circuitry of real hardware (along with the usu…

> It's also not a total solution: by taking many more transistors to programmatically simulate just one, it limits the maximum scale and frequency of what it can support. N64/PS1/Saturn has not yet been fully supported and is still theoretical, but likely, to be possible. Going beyond that is not possible at this time. The limiting factor here is the amount of stuff you can throw into a single FPGA, correct? So in th…

> The limiting factor here is the amount of stuff you can throw into a single FPGA, correct?

And the speed that you can get your design to run at. Something like the Game Cube (PPC750 @ 485 MHz) would be difficult to implement in an FPGA, for example.

Re: MiSTer, an open-source FPGA gaming project

#34

Post by GekkePrutser »

near wrote: post #6
GekkePrutser wrote: post #2

This isn't really new, right? I've heard of this years ago. But it is an amazing project. Instead of emulating, they actually rebuilt the old custom ICs (which 8-bit computers were full of) in an FPGA. Really impressive.

It is indeed an amazing project, especially its open source nature. It provides some impressive power savings and latency reductions that are very hard to match with general purpose CPUs. But in most cases, it is emulation, as the lead developer will attest. https://github.com/MiSTer-devel/Main_MiSTer/wiki/Why-FPGA "From my point of view, if the FPGA code is based on the circuitry of real hardware (along with the usu…

Ah ok I wasn't aware of this. I thought it was spot on.

And yeah I hope we can easily order small batches of ICs (at big pitch of course) in a few years, in a similar way to how creating PCBs has become so simple now.

I mean I remember how much of a PITA it was in the 80s. Drawing on overhead sheets. All the acids and other chemicals. Drilling. And now we get super-accurate 10x10cm boards dual-layer, drilled, soldermasked and silkscreened for a buck a pop with a minimum of 10. Wow. I really hope this trend continues down to the scale of ICs (or that FPGAs simply get better/easier).

By the way, emulating a CPU is pretty easy and very accurate anyway. The big problem with accurate emulation is with some of the peripheral ICs which used hard to emulate stuff like analog sound generators.

Re: MiSTer, an open-source FPGA gaming project

#35

Post by cmrdporcupine »

stormbrew wrote: post #19
jamespo wrote: post #13

Earlier quoted context omitted.

So it's not perfect but it's better than emulators...

I'm really curious where you got "better" out of the quoted text. Because it's not there or implied, but people keep reading this into anything about fpga recreations of chips. There's nothing inherently better about doing emulation on an fpga or a cpu, other than basically the amount of electricity involved in doing it. But people keep presuming an improved accuracy that there's no basis for.

Lower latency is definitely a thing. With FPGA it's possible to 'chase the beam' like the original hardware, and have much reduced input latency from devices, etc. With an emulator you're going to be fighting the OS and the frameworks you built on top of. Even if you go "bare metal" (like my friend's BMC64 project which runs a C64 emulator like a unikernel on the RPi with no OS) you are still dealing with hardware built for usage patterns very different from the classic systems. You're always going to be one or more frames behind.

Re: MiSTer, an open-source FPGA gaming project

#36

Post by FPGAhacker »

near wrote: post #21
mbalyuzi wrote: post #20

Earlier quoted context omitted.

Actually decapping the original chips is very much a thing. See for example Chris Smith's work mapping out the innards of the ZX Spectrum ULA - http://www.zxdesign.info/book/insideULA.shtml .

It is, but these cores are almost exclusively not being done that way. Not yet at least. I hope that they will be, that would be really awesome. I paid $1200 last year for the SNES PPUs to be decapped for this purpose, but it's a truly enormous undertaking to map out those chips and then recreate it in Verilog. You're talking thousands of hours of work per chip. If anyone reading this is able to help with that effort…

Not that this is necessarily helpful to you in the short term, but it strikes me as a good problem for machine learning (going from die pictures to transistor schematic.)

Re: MiSTer, an open-source FPGA gaming project

#37

Post by near »

cmrdporcupine wrote: post #35
stormbrew wrote: post #19

Earlier quoted context omitted.

I'm really curious where you got "better" out of the quoted text. Because it's not there or implied, but people keep reading this into anything about fpga recreations of chips. There's nothing inherently better about doing emulation on an fpga or a cpu, other than basically the amount of electricity involved in doing it. But people keep presuming an improved accuracy that there's no basis for.

Lower latency is definitely a thing. With FPGA it's possible to 'chase the beam' like the original hardware, and have much reduced input latency from devices, etc. With an emulator you're going to be fighting the OS and the frameworks you built on top of. Even if you go "bare metal" (like my friend's BMC64 project which runs a C64 emulator like a unikernel on the RPi with no OS) you are still dealing with hardware bu…

That is true. There are however techniques software emulators can use like run-ahead that can get you lower latency than even the original hardware on a PC: https://near.sh/articles/input/run-ahead

The caveat is that it doesn't always work, and it makes the power requirements even more unbalanced. Some might also see it as a form of cheating to go below the original game's latency. If you want to match the original game's latency precisely, FPGAs are the way to go right now for sure.

Re: MiSTer, an open-source FPGA gaming project

#38

Post by vardump »

near wrote: post #32
mschuster91 wrote: post #30

Earlier quoted context omitted.

> It's also not a total solution: by taking many more transistors to programmatically simulate just one, it limits the maximum scale and frequency of what it can support. N64/PS1/Saturn has not yet been fully supported and is still theoretical, but likely, to be possible. Going beyond that is not possible at this time. The limiting factor here is the amount of stuff you can throw into a single FPGA, correct? So in th…

There's both a cost and a speed barrier to it. FPGAs are often used to design, simulate, and test modern circuits at sub-realtime speeds. No amount of FPGAs will get you a PS2 emulator at playable speeds right now, let alone a PS3/Switch emulator. PCs can do that today by taking shortcuts such as dynamic recompilation and idle loop skipping.

Hmm... looking at the frequencies and gate counts, I think PS2 is well within realm of possibility to run on a not-so-cheap FPGA (or several). But PS3 generation consoles definitely not.

Re: MiSTer, an open-source FPGA gaming project

#39

Post by tediousdemise »

near wrote: post #21
mbalyuzi wrote: post #20

Earlier quoted context omitted.

Actually decapping the original chips is very much a thing. See for example Chris Smith's work mapping out the innards of the ZX Spectrum ULA - http://www.zxdesign.info/book/insideULA.shtml .

It is, but these cores are almost exclusively not being done that way. Not yet at least. I hope that they will be, that would be really awesome. I paid $1200 last year for the SNES PPUs to be decapped for this purpose, but it's a truly enormous undertaking to map out those chips and then recreate it in Verilog. You're talking thousands of hours of work per chip. If anyone reading this is able to help with that effort…

By decapped, do you mean delidded?

Theoretically it would be possible to automate this with a couple things:

- USB electron microscope to image the transistor topology

- CV lib to identify connections and generate corresponding Verilog code

Re: MiSTer, an open-source FPGA gaming project

#40

Post by klodolph »

tediousdemise wrote: post #24
TillE wrote: post #16

Earlier quoted context omitted.

byuu wrote a good article about this, unfortunately it's no longer available, but basically it should be self-evident that there's nothing inherently more accurate about hardware emulation. If you've actually decapped the original chips and duplicated them exactly in an FPGA, that's pretty cool. But otherwise it's just another approximation. The lower power requirements are nice, of course.

On FPGAs (depending on the hardware mapping), you get the benefit of lower latency. I consider this to be timing accuracy. Say you have two implementations of an LED controlled by a switch: one which uses an FPGA and one which uses a microcontroller. The uC implementation must continuously poll peripherals connected to its GPIO pins at a set frequency; it must check the state of the switch, and then change the state…

Most game consoles don’t do any of this, though. The gamepad is polled by software.

On the NES and SNES, the buttons are connected to a shift register (e.g. 4021). The CPU triggers a latch and then reads out the shift register one bit at a time.

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