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MIPS Becomes RISC-V

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131–140 of 225 posts

Re: MIPS Becomes RISC-V

#131
post #88

Earlier quoted context omitted.

Check your router's CPU. I own 4 routers and all of them use MIPS. RISC-V is more like Graphene, it's yet to leave the lab.

> it's yet to leave the lab. You can buy them on Amazon. https://www.amazon.com/dp/B08W2J9B8J https://www.mouser.com/ProductDetail/?qs=pUKx8fyJudB1sOWbbEn...

> You can buy them on Amazon.

> Currently unavailable. We don't know when or if this item will be back in stock.

Clearly not!

Re: MIPS Becomes RISC-V

#132
I started assembly programming on early x86 chips. Then I landed a job programming MIPS chips.

They were so much easier to work with in assembler than x86.

I was quite impressed.

Then came the SGI Indy for me. Good times.

Sorry to see them go.

Re: MIPS Becomes RISC-V

#133
post #88

This is more or less analogous to Blackberry moving to Android, isn’t it? Storied, old-guard tech company loses most of its market share, trades in its first-party stack for a rising open-source alternative. Is MIPS still a big enough name to make this much of a coup for RISC-V? Or is this the last-ditch effort of a fallen star of the semi market?

Check your router's CPU. I own 4 routers and all of them use MIPS. RISC-V is more like Graphene, it's yet to leave the lab.

Most newer generation, upcoming replacement of lower cost SKUs, including NAS are all going to ARM.

At one point there were a few more MIPS and even OpenPOWER solution on NAS and router, but at the end having everything on ARM is just so much easier. Little sad to see it go. Especially good old Broadcom MIPS tends to be exceptionally stable.

Re: MIPS Becomes RISC-V

#134

There's a lot to like about MIPS. It's a perfectly usable RISC architecture that: - is easy to implement - is supported by Debian, gcc, etc.. - is virtualizable - scales from embedded systems (e.g. compressed MIPS16 ISA) up to huge shared-memory multiprocessor systems with hundreds of CPUs Like RISC-V, MIPS traces its lineage to the dawn of the RISC revolution in the 1980s, though on the Hennessy/Stanford side rather…

There is no, one, MIPS ISA. They've been through a number of incompatible changes over the years. MIPS r6 added some things more like RISC-V. NanoMIPS loops even more like RISC-V, though with its own twist (and with some 48 bit instructions, which RISC-V doesn't have yet).

In many ways modern MIPS and RISC-V are pretty much just different binary encodings of the same ideas.

In 2010 MIPS wanted $2 million from Berkeley to allow them to use the MIPS instruction encodings for processor cores that Berkeley would design entirely themselves. So they made up their own encodings instead.

The rest is history.

Re: MIPS Becomes RISC-V

#135

There's a lot to like about MIPS. It's a perfectly usable RISC architecture that: - is easy to implement - is supported by Debian, gcc, etc.. - is virtualizable - scales from embedded systems (e.g. compressed MIPS16 ISA) up to huge shared-memory multiprocessor systems with hundreds of CPUs Like RISC-V, MIPS traces its lineage to the dawn of the RISC revolution in the 1980s, though on the Hennessy/Stanford side rather…

- the NOP instruction is 0x0 :)

RISC-V deliberately made sure both all 0s and all 1s are forever illegal instructions, in all instruction lengths.

Re: MIPS Becomes RISC-V

#136
post #53

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

I'm curious if someone could explain the architectural differences between ppc64le and aarch64? I've always heard they are quite similar.

MIPSr6, aarch64 and riscv are siblings born from MIPSr5 plus the best of other RISC architectures.

ppc64le and 32-bit Arm are part of the wider family, but have some notable differences that make them slightly less RISC-like. Both include e.g. more complex condition code handling and instructions that operate on more than three registers.

Re: MIPS Becomes RISC-V

#137
In 2010 MIPS wanted $2 million from Berkeley to allow them to use the MIPS instruction encodings for processor cores that Berkeley would design entirely themselves. So they made up their own encodings instead.

The rest is history.

In many ways modern MIPS and RISC-V are pretty much just different binary encodings of the same ideas.

[this was already posted as a comment in a thread, but on reflection it probably deserves its own]

Re: MIPS Becomes RISC-V

#139

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

>Power/PowerPC is still out there somewhere though.

https://openpowerfoundation.org

https://github.com/antonblanchard/microwatt

Unfortunately it isn't gaining any traction. From a Long term Cost perspective it is actually cheaper choosing ARM even if OpenPOWER is free. And ARM is already inexpensive.

Re: MIPS Becomes RISC-V

#140

Earlier quoted context omitted.

- the NOP instruction is 0x0 :)

RISC-V deliberately made sure both all 0s and all 1s are forever illegal instructions, in all instruction lengths.

Wasm too. Bytecode 0 is "unreachable" and executing it produces a trap.
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