Hats off to people who do this kind of work. However... *clears throat* I have real trouble using the term "research" for something like this, lumping it together with activities such as "research" in natural science, "research" in anthropology, or even journalistic "research". The difference to me is that this activity could be "done", or rather entirely avoided, if Apple didn't decide to keep it a secret. Mind you,…
Your comment reminds me of a scifi story (Greg Egan maybe?) where AI has taken the lead on science, and humanity's scientists' job is now just to understand the AI's discoveries.
Apple M1 Microarchitecture Research
31–40 of 52 posts
Re: Apple M1 Microarchitecture Research
#32Warehouse: unified memory Workshop: CPU, GPU and other cores Products (raw materials): information, data there's also a new unified memory architecture that lets the CPU, GPU, and other cores exchange information between one another, and with unified memory, the CPU and GPU can access memory simultaneously rather than copying data between one area and another. Accessing the same pool of memory without the need for copying speeds up information exchange for faster overall performance. reference: Developer Delves Into Reasons Why Apple's M1 Chip is So Fast
From the introduction Apple M1 has not done global optimization of various core (workshop) scheduling. Apple M1 only optimizes the access to memory data (materials and products in the warehouse). Apple needs to further improve the programming language and compiler to support and promote my programming methodology. My architecture supports a wider range of workshop types than Apple M1, with greater efficiency, scalability and flexibility. Conclusion Apple M1 chip still needs a lot of optimization work, now its optimization level is still very simple, after all, it is only the first generation of works, released in stages. Forecast(2021-01-19): I think Intel, AMD, ARM, supercomputer, etc. will adopt the "warehouse/workshop model"
In the past, the performance of the CPU played a decisive role in the performance of the computer. There were few CPU cores and the number and types of peripherals. Therefore, the CPU became the center of the computer hardware architecture.
Now, with more and more CPU and GPU cores, and the number and types of peripherals, the communication, coordination, and management of cores (or components, peripherals) have become more and more important, They become a key factor in computer performance.
The core views of management science and computer science are the same: Use all available resources to complete the goal with the highest efficiency. It is the best field of management science to accomplish production goals through communication, coordination, and management of various available resources. The most effective, reliable, and absolutely mainstream way is the "warehouse/workshop model".
Only changing the architecture, not changing or only expanding the CPU instruction set, not only will not affect the CPU compatibility, but also bring huge optimization space.
So I think Intel, AMD, ARM, supercomputing, etc. will adopt the "warehouse/workshop model", which is an inevitable trend in the development of computer hardware.
Finally, "Warehouse/Workshop Model" and "Von Neumann Architecture" will become the two major architectures in the IT field.
https://github.com/linpengcheng/PurefunctionPipelineDataflow...
Re: Apple M1 Microarchitecture Research
#33It's interesting work. The results show a marked contrast with equivalent information for Intel (think uops.info, Agner Fog's work or even the Optimization Reference Manual). Most obvious is separating general purpose register stuff from SIMD. If you have a mixed workload, this means M1 is much wider in that sense (although note that the SIMD registers involved are 128b as opposed to up to 512b). Intel's execution po…
Re: Apple M1 Microarchitecture Research
#34That’s an impressive piece of work. I would love to know how far this is from the information in the actual internal documentation. It’s very nice to have some excitement about a mainstream CPU architecture again.
Just a pain that due to Apple's policies on keeping a big margin and lack of sharing technology means that the rest of the industry won't benefit from this. Still very hard to see not getting an M1 as my next laptop, especially if they continue to do sane things line remove the shitty touchbar.
Re: Apple M1 Microarchitecture Research
#35Earlier quoted context omitted.
Just a pain that due to Apple's policies on keeping a big margin and lack of sharing technology means that the rest of the industry won't benefit from this. Still very hard to see not getting an M1 as my next laptop, especially if they continue to do sane things line remove the shitty touchbar.
Nuvia (former Apple M1 team members) was acquired by Qualcomm, so hopefully new laptop SoCs are on the way.
So instead of having Wintel/Mac we’ll have Wincomm/Mac or Wintel/Wincomm/Mac; not sure it’ll be much better.
Re: Apple M1 Microarchitecture Research
#36Hats off to people who do this kind of work. However... *clears throat* I have real trouble using the term "research" for something like this, lumping it together with activities such as "research" in natural science, "research" in anthropology, or even journalistic "research". The difference to me is that this activity could be "done", or rather entirely avoided, if Apple didn't decide to keep it a secret. Mind you,…
Re: Apple M1 Microarchitecture Research
#37Source for what a validation buffer is? Couldn't find a reference on google
They say the M1 may use a validation buffer instead of a re order buffer. This makes it somewhat clear if you know what a re order buffer is. Processors basically do this: read instructions, execute them out of order to fully use cpu resources, put the instructions back in order along with their results, and then write results to memory. This way the “final state” follows the order of instructions. The “put back in o…
Basically the whole, "put it back in order" bits only have to happen around memory barriers because the visibility of writes isn't guaranteed otherwise.
Whether this matters given large write combining/writeback buffering that queues up early writes until the later writes have completed is one of those decade+ long arguments.
Re: Apple M1 Microarchitecture Research
#38Earlier quoted context omitted.
Nuvia (former Apple M1 team members) was acquired by Qualcomm, so hopefully new laptop SoCs are on the way.
Yeah but Qualcomm... They’re perfectly happy sitting in their arses if there’s nobody to kick them around, and they’re just a nuisance generally. I hope I’m wrong, but they won’t have direct competition from Apple because it looks unlikely that M1 devices will run Windows. They seem to be more or less happy with being 2 generations behind Apple on phone SoCs. And they basically gave up on wearables. So instead of hav…
It was under Parallels but I’m sure over time someone will figure out how to direct boot into it if that’s really important.
Performance of the M1 running Windows and games either in Crossover (commercial WINE implementation - well worth the $40 for ease of use/installation) or the Windows 10 beta actually turned out to be a bad thing. I subscribe to way too many assets in Cities:Skylines to use 16GB of RAM - I need at least 32GB so with great difficulty I returned the 16GB MBA and am eagerly awaiting the next round of AS Macs, hoping there will be at least one laptop that can take at lease 32GB of RAM. If so I will probably never update my Windows gaming machine again. Not that I could if I wanted to right now with the insane GPU shortages - but that’s another topic :p
Re: Apple M1 Microarchitecture Research
#39Earlier quoted context omitted.
They say the M1 may use a validation buffer instead of a re order buffer. This makes it somewhat clear if you know what a re order buffer is. Processors basically do this: read instructions, execute them out of order to fully use cpu resources, put the instructions back in order along with their results, and then write results to memory. This way the “final state” follows the order of instructions. The “put back in o…
The Sun Microsystems Rock processor had I guess, validation? Rather than re-order instructions, you just speculatively execute instructions, issue you memory ops but don't stop and wait, called "hardware scouting". If after everything resolves, you find your prediction was wrong, you rollback. So it's a kind of Transactional Memory approach, and if validation fails, you re-execute the same sequence of instructions, b…
Re: Apple M1 Microarchitecture Research
#40It's interesting work. The results show a marked contrast with equivalent information for Intel (think uops.info, Agner Fog's work or even the Optimization Reference Manual). Most obvious is separating general purpose register stuff from SIMD. If you have a mixed workload, this means M1 is much wider in that sense (although note that the SIMD registers involved are 128b as opposed to up to 512b). Intel's execution po…
Intel's more likely argument is that they can't do that many because their decoders and ROB aren't wide enough to keep up. Given how huge their decode units are (about as big as all their integer ALUs), I don't know how x86 will actually solve this issue.