It's interesting work. The results show a marked contrast with equivalent information for Intel (think uops.info, Agner Fog's work or even the Optimization Reference Manual).
Most obvious is separating general purpose register stuff from SIMD. If you have a mixed workload, this means M1 is much wider in that sense (although note that the SIMD registers involved are 128b as opposed to up to 512b).
Intel's execution ports tend to be special flowers - there's almost always stuff that can be done and can't be done on any given port. So, of the execution ports (0,1,5,6) each one tends to have some special flavor that the others don't share - and there are often complex "oh, you can only do 2 of those or 3 of these". There's a very small list of operations (generally logic and LEA) that can be done on all of 0,1,5,6.
By contrast, most of the M1 things, you can do across every unit that is capable of doing it. Want to do 4 SIMD math ops? Go for your life! It's certainly easier to remember and understand.
I imagine the counterargument on the Intel side is that it's unlikely you need that many of some given operation - so they are saving area to not make every port omni-capable. This works pretty well (right up to the point it doesn't).
It will be interesting to see how the comparison between Intel and Apple plays out in the near future. M1 is a tour de force of balanced design, but I wouldn't count Intel out - especially if they can get their process mojo back (a lot of M1's current advantage is being able to invest transistors in a balanced and sensible way across the entire pipeline due to a better process).