Earlier quoted context omitted.
Not necessarily; physical size matters a lot. Just an example: consider you were to add some extra electrical charge to the gate of a transistor (from an electron or ion beam, I don't know). A larger transistor has a higher gate capacitance, it is therefore quite immune against a few extra charges. On smaller transistors, though, it could dramatically increase the voltage, leading to a bit error, or destroying the tr…
This raises the question, why not simply continue to make larger circuits today for this purpose? Surely we could still make a chip today with the same transistor size as one from 2001, but better in other ways.
In microelectronics, costs are directly proportional to the die area. Actually, they might rise faster due to yield issues.
Making masks [1] is expensive. The bigger the mask, the more expensive. A mask set for a modern CPU can easily be in the millions, I think. And it gets more expensive with size.
Then you have yield. The bigger the chip, the more likely it has some defects (due to dust or other issues during fabrication). Often, processes work more or less well across a wafer: temperature higher in the center, etc. That can affect performance.
Due to yields, bigger chips have to be scrapped more often, and are generally less performant. Binning (selecting the fastest, slowest, more efficient, or chips with specific intact features across a wafer) is less effective. You might have to add redundancy or mechanisms to cut power to damaged areas to avoid short circuits.
Now, that's why we don't generally make bigger integrated circuits. Now, we could make bigger integrated circuits with today's latest clean rooms and equipment to try to raise yields. I don't know if that's being done already, but it would likely raise costs. On the other hand, progress is being made on bigger chips as well [2].
Another more promising direction (IMO) is to use chiplets like AMD does it. You could use more of these for a bigger virtual size.
Now, like I wrote, a lot of the performance improvements actually come down from physically scaling down the transistors: if the gate is smaller, the transistor needs less electrons to charge up. That means faster transistors, and less energy. Also, transistors are closer, so signals reach the next one faster [3].
If you want bigger chips at a previous technological node, you are going to need a huge heatsink, or disable part of the chip ("dark silicon") [4].
The real answer might come from completely different architectures, based on light or spin, or more power-efficient circuit/computer architectures like with adiabatic computing [5] (or non von neumann based, closer to what I do).
Power efficiency is key, since that's the limiting factor for performance nowadays (ask any overclocker: you don't want to melt your CPU. Also, rovers have a small energy budget). With better efficiency, you have room to grow performance again.
Paradoxally, software seems headed in the other direction, generally speaking.
[1] https://en.wikipedia.org/wiki/Photomask
[2] https://news.ycombinator.com/item?id=20739408
[3] https://en.wikipedia.org/wiki/Dennard_scaling