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Architecture of the Playstation 2

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Re: Architecture of the Playstation 2

#31

Post by gumby »

I remember when Toshiba first showed us the R5900, which was a real screamer for its time. They couldn’t tell us at first whom they were designing it for. This was perhaps 2-3 years before the PS2 was publicly announced (at, IIRC, E3) and even before it had been discussed with any 3P developers.

In fact the secrecy before it was released was insane. Toshiba and Sony kept their technology very close to their chest and each would tell us stuff under NDA that prevented us from talking to the other about it.

I sometimes wondered if we were the only folks who could see both sides. On a couple of occasions we had to delicately get permission / forgiveness for slightly bending NDA to make sure that some misunderstanding could be resolved (think of two companies building a bridge, owithout looking across the river to see where the other guys are aiming).

Ken Kutaragi was (still is I imagine) an inspired thinker and leader and good supporter. He built a great team, some of whom are still friends.

One of the great, if grueling experiences of my life.

Re: Architecture of the Playstation 2

#32

Post by monocasa »

kmeisthax wrote: post #26
paulmd wrote: post #23

Earlier quoted context omitted.

Cell was a disappointment in the PS3 though. It was such an underperformer that the SPEs couldn’t be used for their intended role as a GPU and got shanghied into being used like SMT cores, while a whole separate GPU chip had to be added into the design at the last minute to compensate. The Cell’s weak CPU performance, strange programming model, and weak developer tooling was a problem for pretty much the whole genera…

Sony wanted high-performace integrated graphics a full generation before such things were really feasible. I think that's ultimately why the CELL was such a failure - it was trying to do way too many things too ineffectively. Also, building a GPU out of multiple tiny CPU cores on a ring bus just seems incredibly wrong. Even back then, the way you built a GPU was to have one instruction stream controlling many ALUs an…

Cell's problem was the end of Dennard scaling hit them as hard as it hit the Pentium 4. It was designed in an era that was expecting to be able to get 5Ghz+ easily out of (albeit premium) consumer electronics chips.

https://en.wikipedia.org/wiki/Dennard_scaling#Breakdown_of_D...

By the time they figured out that they weren't going to be able to cash the metaphorical checks the process side had been writing up until that point, it was too late to go back to square one. The design unfortunately had to be pigeon holed out of it's designed niche, and they had to strap that anemic Nvidia GPU to the side of it just to have a shippable product. Turned out really well given all those factors working against it.

Re: Architecture of the Playstation 2

#33

Post by p_l »

corysama wrote: post #13
rtpg wrote: post #8

I remember reading some story way back with some ... Sony exec? Someone saying that there were people writing engine code in Excel to be able to track the co processors and get the timing right. Does anyone know of the truthiness of such a story? I'm learning FPGA design and even there, when timing is pretty controlled, people end up recommending design patterns where you gate stuff similar to how you would do it in…

I bet they were writing Vector Unit assembly in Excel. The VLIW design meant that you literally packed 2 assembly instructions together into a 64-bit word. Each side had it's own subset of execution units it could utilize and would have it's own separate latency for each operation. So, to keep track of everything going on you pretty much had to write out two columns of code containing your own no-op notation to repre…

The story I heard was of a very, very heavily macro-based excel sheet that would automatically highlight possible problems including pipeline stalls in one of the VLIW units.

Been looking for confirmation or just a screenshot of that monster since :D

Re: Architecture of the Playstation 2

#34

Post by h0l0cube »

rtpg wrote: post #8

I remember reading some story way back with some ... Sony exec? Someone saying that there were people writing engine code in Excel to be able to track the co processors and get the timing right. Does anyone know of the truthiness of such a story? I'm learning FPGA design and even there, when timing is pretty controlled, people end up recommending design patterns where you gate stuff similar to how you would do it in…

It might have made things simpler. From memory there was also a VU compiler that would take a single stream of instructions and then try to interleave the the 'left/right' instructions of the VLIW in the most efficient orders. It never was quite as good as hand coding - which is something kind of satisfying once you've memorized the stats of the entire ISA.

One half of the instruction word was mostly devoted to vector instructions which would each have a 4 cycle latency, and a single cycle throughput, to say, multiple one 4 word vector of floats with another. The other half had the kitchen sink, like trancendental functions (sin/cos/tan/etc), divide (x/y, 1/x), etc. However an instruction would stall if a calculation was depending on a register whose calculation was still in flight.

So if an instruction has a latency of 4 cycles, you could interleave 4 similar calculations on more of the dataset in parallel. So in 4 cycles, you could start 16 float calculations, and by the 8th cycle, they would be available. Though likely you'd be looping with something like Duff's device to maximize throughput. It would also mean you might use the vector calculations with a taylor series, in preference to the sine instruction which had a latency of something like 15 cycles.

Re: Architecture of the Playstation 2

#36

Post by deergomoo »

blodkorv wrote: post #35

Despite its advanced and complicated design it was outpreformed pretty easily by more general purpose cpus that where not nessicarily much newer.

Including the Xbox and GameCube. Well, the Xbox was built out of significantly more "general purpose" parts than the GameCube, but both still handily outperformed the PS2.

Re: Architecture of the Playstation 2

#38

Post by rusk »

I ran across an interesting factoid a while back where a line was drawn between the Amiga CD32 and PS2 - that somehow Sony picked up where Commodore left off but I’ve been unable to find a reference since and I’m certain at this stage I’ve got the names and dates mixed up ... anyone heard anything like this?

Re: Architecture of the Playstation 2

#39

Post by swebs »

deergomoo wrote: post #36
blodkorv wrote: post #35

Despite its advanced and complicated design it was outpreformed pretty easily by more general purpose cpus that where not nessicarily much newer.

Including the Xbox and GameCube. Well, the Xbox was built out of significantly more "general purpose" parts than the GameCube, but both still handily outperformed the PS2.

I'm really surprised how the Gamecube was able to run circles around the PS2, despite being cheaper and using just a standard CPU/GPU combo.

Re: Architecture of the Playstation 2

#40

Post by girvo »

mhh__ wrote: post #11
rtpg wrote: post #8

I remember reading some story way back with some ... Sony exec? Someone saying that there were people writing engine code in Excel to be able to track the co processors and get the timing right. Does anyone know of the truthiness of such a story? I'm learning FPGA design and even there, when timing is pretty controlled, people end up recommending design patterns where you gate stuff similar to how you would do it in…

Excel as in microsoft excel!?

I can totally see it working well for writing in columns, and being able to do rudimentary automated analysis!
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