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The CPUs of Spacecraft Computers in Space

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Re: The CPUs of Spacecraft Computers in Space

#51

Post by bumby »

inamberclad wrote: post #8
dimator wrote: post #5

Earlier quoted context omitted.

My understanding is that certification is the bottle neck, in both time and cost. No one wants to spend the money or time to flight certify something new when something already battle tested will suffice. But your comment makes me wonder if the private sector doesn't have those certification requirements? The other differentiating factor is that the private sector is not sending multi-year (indeed multi-decade) deep…

To answer - no we don't have the same certification requirements. NASA steps in when there's human lives and/or a lot of money on the line, but most smaller projects and just about every independent project is free to assume its own level of risk.

You know (and probably are implying) this but it’s completely program/project specific. Some projects out of Armstrong, for example, must meet FAA certification requirements

Re: The CPUs of Spacecraft Computers in Space

#52

Post by mhh__ »

bumby wrote: post #50
mhh__ wrote: post #47

Earlier quoted context omitted.

> Starlink with Xilinx FPGAs, while NASA and DoD are still baselining new platforms on incredibly expensive (albeit rad-hard) PowerPC RAD750 and similar. Ignoring that Starlink isn't very far away, I would assume NASA stuff would also have FPGAs and ASICs on them - they aren't CPUs and aren't used like them.

Some NASA orgs have tried using FPGAs as a way to get around software requirements, to varying levels of success

Interesting, although I was more thinking about FPGA's in things like acquisition and processing rather than overall logic as the PC seemed to imply.

Re: The CPUs of Spacecraft Computers in Space

#53

Post by bumby »

mhh__ wrote: post #52
bumby wrote: post #50

Earlier quoted context omitted.

Some NASA orgs have tried using FPGAs as a way to get around software requirements, to varying levels of success

Interesting, although I was more thinking about FPGA's in things like acquisition and processing rather than overall logic as the PC seemed to imply.

The high level NASA requirements cast a pretty wide net (to include data acquisition and processing) as to what falls under the purview of those requirements. From 7150.2:

“ A.30 Software. Computer programs, procedures, scripts, rules, and associated documentation and data pertaining to the development and operation of a computer system. Software includes programs and data. This also includes COTS, GOTS, MOTS, reused software, auto generated code, embedded software, firmware, and open source software components.”

https://nodis3.gsfc.nasa.gov/displayCA.cfm?Internal_ID=N_PR_...

Re: The CPUs of Spacecraft Computers in Space

#54

Post by [deleted] »

dylan604 wrote: post #30
dimator wrote: post #5

Earlier quoted context omitted.

My understanding is that certification is the bottle neck, in both time and cost. No one wants to spend the money or time to flight certify something new when something already battle tested will suffice. But your comment makes me wonder if the private sector doesn't have those certification requirements? The other differentiating factor is that the private sector is not sending multi-year (indeed multi-decade) deep…

How do you battle test a RAD prototype? Stick it in microwave like device with ionizing radiation and see how many bit-flips occur?

[deleted]

Re: The CPUs of Spacecraft Computers in Space

#55

Post by quazar987 »

verberant wrote: post #3

Space flight computers in the public sector are generally 15-20 years behind the types of hardware we commonly work with on the ground, as I think this page shows. We now have pretty capable low-power SoCs and FPGAs that we've yet to see broadly leveraged for govt. space applications. SpaceX flies Starlink with Xilinx FPGAs, while NASA and DoD are still baselining new platforms on incredibly expensive (albeit rad-har…

There’s more to it than just specs. Consumer grade silicon will not survive in space, radiation will just kill them.

Re: The CPUs of Spacecraft Computers in Space

#56

Post by trzy »

kevin_thibedeau wrote: post #43
cpgxiii wrote: post #15

Earlier quoted context omitted.

The RAD750 (edit - the whole RAD family, there are newer models available) remains the standard because it's the highest performance rad-hard design available, period. If you're putting an expensive satellite in orbit for 5,10 years, the cost of the processors is insignificant compared to everything else. The real problem is that we don't have good solutions for improving the performance of rad-hard designs, so we're…

I had to select a processor that controls the camera in the GOES-R ABI. The image processing is all done by custom hardware so all that was needed was microcontroller level performance. It turns out there are very limited options in this space and all of them are quirky outdated architectures with limited available tooling. The RAD750 in particular is a bit of a nightmare because of the high pin count, need for a sup…

How does the PowerPC’s reverse bit numbering impact power consumption?

Re: The CPUs of Spacecraft Computers in Space

#57

Post by sephamorr »

phire wrote: post #40
FredFS456 wrote: post #38

Earlier quoted context omitted.

Low Earth Orbit (LEO) which the ISS is in is very different from deep space. You can get away with much less radiation hardening in LEO. For example, I know a company consumer-grade Xilinx MPSoCs with 4xA53 cores at 1.5GHz.

They literally ship off the shelf laptops and smartphones to the ISS. They do modify them slightly to remove the lithium-ion batteries, which you do not want inside a space craft. I think they replace them wit NiMH cells if the devices still need to be battery powered.

They no longer do this, and are now happy with just testing li ion products. There are iPads all over the station (and used by the astronauts on the SpaceX Dragon)

Re: The CPUs of Spacecraft Computers in Space

#58

Post by kevin_thibedeau »

trzy wrote: post #56
kevin_thibedeau wrote: post #43

Earlier quoted context omitted.

I had to select a processor that controls the camera in the GOES-R ABI. The image processing is all done by custom hardware so all that was needed was microcontroller level performance. It turns out there are very limited options in this space and all of them are quirky outdated architectures with limited available tooling. The RAD750 in particular is a bit of a nightmare because of the high pin count, need for a sup…

How does the PowerPC’s reverse bit numbering impact power consumption?

If you wire the bits as numbered to a conventional memory device designed with LSB as bit-0, the internal address bus will induce more switching from sequential access than normal. The internal row and column decoders will be working overtime consuming more power than necessary. Reversing the bus to deal with that isn't always straightforward on a space constrained board.

Re: The CPUs of Spacecraft Computers in Space

#59

Post by trzy »

kevin_thibedeau wrote: post #58
trzy wrote: post #56

Earlier quoted context omitted.

How does the PowerPC’s reverse bit numbering impact power consumption?

If you wire the bits as numbered to a conventional memory device designed with LSB as bit-0, the internal address bus will induce more switching from sequential access than normal. The internal row and column decoders will be working overtime consuming more power than necessary. Reversing the bus to deal with that isn't always straightforward on a space constrained board.

If I understand correctly, you are saying that with the reversed bit numbering, bit 31 (in a 32-bit address bus) changes most frequently with sequential accesses because it is the LSB but when wired to the MSB of SRAM, it causes switching in the column decoder for every single access.

That makes sense but I didn’t realize that it was difficult to simple swap the wiring. Are the physical pins ordered backwards as well (that is, do PowerPC’s A31 and A30 appear where A0 and A1, respectively, would be on a “normal” system)?

Re: The CPUs of Spacecraft Computers in Space

#60

Post by sanxiyn »

wiz21c wrote: post #2

What about chinese/indian/japanese spacecrafts ?

China's Chang'e 4 lander is known to use ATMEL AT697F. It is SPARC-compatible.

Source: The scientific objectives and payloads of Chang'e 4 mission. DOI 10.1016/j.pss.2018.02.011. No free source, use Sci-Hub.

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