The CPUs of Spacecraft Computers in Space
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The CPUs of Spacecraft Computers in Space
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Re: The CPUs of Spacecraft Computers in Space
#2What about chinese/indian/japanese spacecrafts ?
Re: The CPUs of Spacecraft Computers in Space
#3Space flight computers in the public sector are generally 15-20 years behind the types of hardware we commonly work with on the ground, as I think this page shows.
We now have pretty capable low-power SoCs and FPGAs that we've yet to see broadly leveraged for govt. space applications. SpaceX flies Starlink with Xilinx FPGAs, while NASA and DoD are still baselining new platforms on incredibly expensive (albeit rad-hard) PowerPC RAD750 and similar. This is a huge bottleneck for any computationally intensive task we might want to do on-orbit, and I'm curious if or when it will change. It's one technical reason, in my opinion, that the private sector is currently calling the shots in space.
Re: The CPUs of Spacecraft Computers in Space
#4ESA uses an OpenSparc fork, LEON.
http://www.esa.int/Enabling_Support/Space_Engineering_Techno...
Re: The CPUs of Spacecraft Computers in Space
#5Space flight computers in the public sector are generally 15-20 years behind the types of hardware we commonly work with on the ground, as I think this page shows. We now have pretty capable low-power SoCs and FPGAs that we've yet to see broadly leveraged for govt. space applications. SpaceX flies Starlink with Xilinx FPGAs, while NASA and DoD are still baselining new platforms on incredibly expensive (albeit rad-har…
My understanding is that certification is the bottle neck, in both time and cost. No one wants to spend the money or time to flight certify something new when something already battle tested will suffice.
But your comment makes me wonder if the private sector doesn't have those certification requirements?
The other differentiating factor is that the private sector is not sending multi-year (indeed multi-decade) deep space missions, where the need for battle tested systems is paramount.
Re: The CPUs of Spacecraft Computers in Space
#6How do these circuits deal with random bit flipping from cosmic rays?
Re: The CPUs of Spacecraft Computers in Space
#7[deleted]
Re: The CPUs of Spacecraft Computers in Space
#8Space flight computers in the public sector are generally 15-20 years behind the types of hardware we commonly work with on the ground, as I think this page shows. We now have pretty capable low-power SoCs and FPGAs that we've yet to see broadly leveraged for govt. space applications. SpaceX flies Starlink with Xilinx FPGAs, while NASA and DoD are still baselining new platforms on incredibly expensive (albeit rad-har…
My understanding is that certification is the bottle neck, in both time and cost. No one wants to spend the money or time to flight certify something new when something already battle tested will suffice. But your comment makes me wonder if the private sector doesn't have those certification requirements? The other differentiating factor is that the private sector is not sending multi-year (indeed multi-decade) deep…
To answer - no we don't have the same certification requirements. NASA steps in when there's human lives and/or a lot of money on the line, but most smaller projects and just about every independent project is free to assume its own level of risk.
Re: The CPUs of Spacecraft Computers in Space
#9How do these circuits deal with random bit flipping from cosmic rays?
The packaging can be different or redundancy can be added to the design: https://en.wikipedia.org/wiki/Radiation_hardening#Radiation-...
Re: The CPUs of Spacecraft Computers in Space
#10How do these circuits deal with random bit flipping from cosmic rays?
There's three basic ways this is done:
1: By process, where chips are created with special or larger features to better resist cosmic rays. This is Expensive since they're made in very low volumes and the cost of the new fab line can't be spread among many millions of units. Instead, a few thousand chips might be made.
2: By design, where redundant systems such as triple redundant memory or voting computers are used. This is probably the most interesting as you can get into issues like the Byzantine Generals problem here. All the redundancy can be implemented in a single FPGA by simply routing out the design 3 times and using voting logic, assuming the FPGA is large enough.
3: By shielding. Just fly regular chips in a shielded box. This causes thermal issues, but is sometimes necessary, such as in Juno, which has to deal with the enormous radiation flux around Jupiter.