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Apple’s A14 Packs 134M Transistors/mm²

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Re: Apple’s A14 Packs 134M Transistors/mm²

#71

Post by eightysixfour »

hinkley wrote: post #64
eightysixfour wrote: post #48

Earlier quoted context omitted.

Sure but, despite the extra space around any individual transistor, you're still shoving 49% more transistors into the same overall amount of space. Then everything benefits and no one cares about the node name.

> you're still shoving 49% more transistors into the same overall amount of space What I fear is that we've hit the point where this is no longer a safe assumption. That we will be having people chase feature size numbers that don't actually result in a proportional increase in chip density. Transistors per square millimeter is closer to a measure we actually care about (speed of light and clock speed) instead of a b…

What from the article makes you think that's no longer a safe assumption? The 49% gain is exactly what happened going to 5nm.

I don't think anyone actually cares about transistors/mm^2 at all, I think what we care about is perf or perf/watt for our specific workloads. I don't care if the chip is built with vacuum tubes if it is fast, efficient (per dollar and watt), and physically fits in the device I want it in.

Re: Apple’s A14 Packs 134M Transistors/mm²

#72

Post by grandmczeb »

samatman wrote: post #60
wmf wrote: post #40

Earlier quoted context omitted.

Apple doesn't have an exclusive on 5 nm; it's also being used by Kirin 9000, Snapdragon 875, some Exynos, and a future Dimensity SoC.

I'm not sure how to square that claim with this sort of article: https://www.extremetech.com/computing/315186-apple-books-tsm...

Snapdragon 875 is 5nm, but on Samsung's process not TSMC's[1].

[1] https://www.techpowerup.com/272139/samsung-foundry-to-become...

Re: Apple’s A14 Packs 134M Transistors/mm²

#73

Post by wmf »

samatman wrote: post #60
wmf wrote: post #40

Earlier quoted context omitted.

Apple doesn't have an exclusive on 5 nm; it's also being used by Kirin 9000, Snapdragon 875, some Exynos, and a future Dimensity SoC.

I'm not sure how to square that claim with this sort of article: https://www.extremetech.com/computing/315186-apple-books-tsm...

There's also Samsung 5 nm.

Re: Apple’s A14 Packs 134M Transistors/mm²

#74

Post by wmf »

exabrial wrote: post #7

For comparison I was trying to nail down what Intel's 7nm process is, but I've found answers between 120nm and 215nm. If anyone knows, that'd be an interesting comparison.

Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 million transistors per square millimeter.

https://en.wikichip.org/wiki/7_nm_lithography_process#P1276

Re: Apple’s A14 Packs 134M Transistors/mm²

#75

Post by FullyFunctional »

Symmetry wrote: post #33
FullyFunctional wrote: post #31

Earlier quoted context omitted.

I'm not sure you are serious, but eDRAM isn't a direct replacement for SRAM. At best it's useful for L3 or L4 cache given the inherently higher latencies. I think we just have to accept that silicon scaling is slowing down.

I was assuming last level cache would be the majority of the usage in this case. Maybe I'm wrong.

For a desktop CPU that wouldn't be far off, but the A14 has a lot of other stuff so I very much doubt that. However, until we see an actual floor plan this is all speculation.

Re: Apple’s A14 Packs 134M Transistors/mm²

#76

Post by m463 »

desiarnezjr wrote: post #65
narrator wrote: post #58

Earlier quoted context omitted.

The funny thing is is this isn't really Apple's achievement. It's TSMC's achievement. It's also Intel's failure in that they failed to get a similar process working on schedule.

Yes, but Qualcomm, Nvidia, AMD and countless others use the same fabs or at least have access to the same fabs. It's Apple's engineering and design.

"Apple Books TSMC's Entire 5nm Production Capability"

https://www.extremetech.com/computing/315186-apple-books-tsm...

so it seems apple paid to get to the front of the line

Re: Apple’s A14 Packs 134M Transistors/mm²

#77

Post by hajile »

ajross wrote: post #35
rdw wrote: post #3

The article says that Apple isn't making full use of the 5nm process node, and blames lack of SRAM scaling for it (presumably due to the large amount of L3 cache). Is this a problem that all processors are about to hit, or is this going to be overcome once process engineers are more familiar with 5nm?

This bit didn't make a lot of sense to me. SRAM is routinely the MOST optimized and MOST worried-over aspect of silicon layout. SRAM cell architectures get hand-optimized carefully years in advance of any process improvements. They aren't just logic that gets spit out of generic tooling. So while it would make sense that a new process would have new design rule that didn't map well to older EDA tooling, it's harder t…

> It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM cells have not been scaling at the same rate as logic in general. At IEDM 2019, the 5nm process was quoted to have 1.84x logic density improvement compared to 1.35x SRAM density improvement[1]

0.021um per cell [1] for TSMC N5 vs 0.027um per cell [0] for TSMC N7.

Even if Apple did everything right, they'd still be behind due to the limits of the process.

[0]https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells...

[1]https://semiwiki.com/semiconductor-manufacturers/tsmc/283487...

Re: Apple’s A14 Packs 134M Transistors/mm²

#78

Post by mucle6 »

Godel_unicode wrote: post #54
jiggawatts wrote: post #32

Earlier quoted context omitted.

I was just looking into optimising a large web application. I told the customer that using a caching layer such as a CDN would help paper over the worst of the inefficiencies in their application and the network stack. That was true! The download times halved. However, benchmarks with F12 developer tools showed that while downloads reduced from 200ms to 100ms, the overall load times were still seconds, of which about…

Sounds like the argument here is "buy an iPad pro so frontend developers don't need to learn optimization"...?

Buy an iPad pro because time and time again we have seen that optimizing is not a priority for the majority of business.

I think the cynicism here is that if only these frontend developers would just learn to optimize we would all finally be better off. I think there are two factors that push against this though. First, if you learn to optimize then you can charge more for your labor, and you will likely get a job somewhere else. Second, companies exist for profit, and optimizing is not often the most profitable next step.

Re: Apple’s A14 Packs 134M Transistors/mm²

#79

Post by robocat »

narrator wrote: post #58
topspin wrote: post #20

I really appreciate this analysis and the straightforward top line number 134e6/mm^2. The usual "node" figure is utterly meaningless; an electrical engineer couldn't care less about "feature" size (whatever that means.) What is the count of discrete components in a given area? There are 40 billion 5nm (the supposed "node" of these chips) squares in a millimeter of area. That's two orders of magnitude more dense than…

The funny thing is is this isn't really Apple's achievement. It's TSMC's achievement. It's also Intel's failure in that they failed to get a similar process working on schedule.

I think you are using black and white thinking: both deserve praise.

Delivering a CPU on a new node process is not a trivial achievement, along with the significant design changes required to achieve the potential gains of the node. Neither is Apple’s business ability to lock in x months of exclusive use of that node. Apple have done an amazing job here, hand in hand with TSMC.

Re: Apple’s A14 Packs 134M Transistors/mm²

#80

Post by m463 »

microtherion wrote: post #37
baron816 wrote: post #28

Would hate to be the guy that had to count all those transistors.

It's not that hard: You just count the pins and divide by 3.

"As of 2019, the highest transistor count in any IC chip is Samsung's 1 TB eUFS (3D-stacked) V-NAND flash memory chip, with 2 trillion floating-gate MOSFETs (4 bits per transistor)."

At 4 bits per transistor and 3 pins, how do you count the samsung bits? :)

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