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TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

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Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#41

Post by agumonkey »

robert_dipaolo wrote: post #28
jmt_ wrote: post #13

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?

der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting; https://youtu.be/uEMDkbF3hu0 https://youtu.be/uXu_1zXOZdY https://youtu.be/_wAeL3f3iV4

With all the electronics and physics chans I binge on youtube I'm surprised this one never hit the suggestion fan, it's utterly fascinating

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#42

Post by ajmarcic »

quag wrote: post #37
jmt_ wrote: post #35

Earlier quoted context omitted.

Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

According to this video using an electron scanning microscope on amd and Intel chips, the “7nm” or “10nm” number does not measure anything, and is effectively a process version number for marketing. From memory there is no single number for measuring transistors or efficiency, transistor density is useful, but it doesn’t tell you the performance or power usage. https://youtu.be/1kQUXpZpLXI

Both performance and power usage are physically functions of transistor density. Assuming the apples-to-apples comparison of similar transistor counts, operating TDPs, and processor designs.

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#43

Post by MayeulC »

phkahler wrote: post #32
swiley wrote: post #27

Earlier quoted context omitted.

That's interesting, I saw a hobbyist photo lithography setup the other year that was able to etch metal with a resolution of 20nm.

That's really not possible. 20um probably. Micro not nano.

Well, nano would be achievable via e-beam lithography, but photolithography is another beast: I'm pretty sure you need EUV at that size, with special (expensive) lenses that do not absorb the UV.

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#44

Post by MayeulC »

quag wrote: post #37
jmt_ wrote: post #35

Earlier quoted context omitted.

Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

According to this video using an electron scanning microscope on amd and Intel chips, the “7nm” or “10nm” number does not measure anything, and is effectively a process version number for marketing. From memory there is no single number for measuring transistors or efficiency, transistor density is useful, but it doesn’t tell you the performance or power usage. https://youtu.be/1kQUXpZpLXI

Moore's law always was an economic roadmap. Everything in the semiconductor industry is (was) planned around the transistor density doubling every two years, from hardware investments, to market segmentation, to microarchitecture design, to software optimizations. So I think it makes sense that they go on with pushing transistor density from generation to generation, and convey it to the public using names it is already familiar with.

It's right that power has severely limited performance despite increasing the transistor density lately. Maybe we'll once again get better with adiabatic computing?

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#45

Post by nitrogen »

hinkley wrote: post #29
reducesuffering wrote: post #22

Earlier quoted context omitted.

This exact scenario is parodied in the show Silicon Valley[0] It's probably fairly commonplace. [0] https://www.youtube.com/watch?v=QZ7m7mV864A

I can never decide if Mike Judge is really this good, or we are really this transparent that a mostly-outsider can peg us so accurately.

Considering how poorly and inaccurately tech is portrayed in most other shows, I'm inclined to believe it's Mike Judge and the people that he chooses to listen to.

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#46

Post by AareyBaba »

Nokinside wrote: post #25
jmt_ wrote: post #13

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?

The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation. The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial…

For perspective, 2nm is approximately how much your fingernail grows in the time it took to read this sentence.

(3.47mm per month)/(30 * 24 * 60 * 60 seconds) = 1.33nm/second

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#47

Post by imtringued »

jmt_ wrote: post #13

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?

The nm process numbers refer to the necessary dimensions of a theoretical planar transistor to achieve the same density as this process. Planar transistors haven't been used for at least a decade. To make matters worse there is no standardized planar transistor design so ultimately you cannot derive any meaning from these numbers other than as a fancy version number that tells you which process is newer. As many others have commented: It's much better to just look at overall transistor density.

FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#48

Post by imtringued »

swiley wrote: post #27
Nokinside wrote: post #25

Earlier quoted context omitted.

The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation. The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial…

That's interesting, I saw a hobbyist photo lithography setup the other year that was able to etch metal with a resolution of 20nm.

State of the art non EUV photo lithography uses light with a 193 nm wavelength. 20nm is significantly below that which would imply usage of highly advanced lithography techniques like multiple patterning. A chip manufactured with a 20nm resolution would involve dozens of masks which were created through electron-beam lithography. Just the mask set alone would cost millions of dollars.

The only hobbyist that I am aware of used a pretty nifty mask less technique but the resolution doesn't come close at all. I think you just mixed up your units.

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#49

Post by jpgvm »

agumonkey wrote: post #41
robert_dipaolo wrote: post #28

Earlier quoted context omitted.

der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting; https://youtu.be/uEMDkbF3hu0 https://youtu.be/uXu_1zXOZdY https://youtu.be/_wAeL3f3iV4

With all the electronics and physics chans I binge on youtube I'm surprised this one never hit the suggestion fan, it's utterly fascinating

der8auer is basically the patron saint of PC overclocking, highly recommend his coverage of new hardware because he goes straight to doing interesting stuff and skips the usual review stuff that everyone else repeats.

Re: TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

#50

Post by megablast »

quag wrote: post #37
jmt_ wrote: post #35

Earlier quoted context omitted.

Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

According to this video using an electron scanning microscope on amd and Intel chips, the “7nm” or “10nm” number does not measure anything, and is effectively a process version number for marketing. From memory there is no single number for measuring transistors or efficiency, transistor density is useful, but it doesn’t tell you the performance or power usage. https://youtu.be/1kQUXpZpLXI

For whom? Surely the people ordering chips know the truth.
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