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Google offers free fabbing for 130nm open-source chips

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Re: Google offers free fabbing for 130nm open-source chips

#11

How much has the power efficiency improved between 130nm and 7nm? Is it plausible to get better performance/watt for a custom chip on 130nm vs a software application running on a 7m chip? I get that hardware has other benefits but just wondering for accelerators where the cost/benefit starts to make sense.

I would definitely be rather interested in learning how to design some chips with feature sizes large enough for power handling... I'd love to hear about this as well. This sounds like a clever way to commoditize hardware design, like when printing PCBs became affordable.

Re: Google offers free fabbing for 130nm open-source chips

#14
With the PDK being open, does anyone know if any kind of NDAs are still required to get a chip fabbed? While free-of-charge fabbing is quite nice, I think being NDA-free is even more important so all work including the tweaks necessary for fabbing can be published, e.g. on GitHub.

BTW, it will be nice to try this together with the OpenROAD tools [1]. They have support for Google's PDK on their to-do list (planned for q3, but I doubt it will be ready that fast).

[1] https://github.com/The-OpenROAD-Project https://theopenroadproject.org/

Re: Google offers free fabbing for 130nm open-source chips

#16

Well done Google. But there is still problem with EDA tool license... Is there any replacement for Cadence Virtuoso tool for chip design?

The efabless people that the talk mentions a bunch of times are using a fully open-source design flow but I think it's a bit hacky (as in, a bunch of command line tools from various open source projects, some of which may be unmaintained judging by the commit logs). They seem to have successfully fabricated a RISC-V based SoC with it though, which is crazy cool.

As somebody with a decent amount of FPGA experience, having a go at setting this software up and seeing if I can get anything to synthesise and through place and route is something I've been intending to have a play with, but I haven't had the spare time.

It uses yosis for synthesis and a few other tools for the rest of the process, and is called Qflow - http://opencircuitdesign.com/qflow/index.html

Re: Google offers free fabbing for 130nm open-source chips

#19

How much has the power efficiency improved between 130nm and 7nm? Is it plausible to get better performance/watt for a custom chip on 130nm vs a software application running on a 7m chip? I get that hardware has other benefits but just wondering for accelerators where the cost/benefit starts to make sense.

You won't be able to profitably mine Bitcoin on 130nm ASICs (just as an example)

130nm is almost 20 years old at this point. You can do amazing things with this process but saving power is probably not one of them.

Re: Google offers free fabbing for 130nm open-source chips

#20
post #2

How "bad" is that compared to standard/common 14nm, etc...

130nm was used to make the Athlon XP, Athlon 64, Pentium M, Pentium 4 and PowerPC G5 in the 2001-2003 timeframe [0]. So at the peak of 130nm's performance spectrum, it was able to produce stuff that can still run 2020 software quite okay. The Athlon 64 is probably the best 130nm silicon produced in its heyday and it's in the ballpark of a Raspberry Pi 4 (which has a 28nm SoC) in single core benchmarks.

I don't think this program is meant or likely to produce high frequency 100mm2+ chips (and it's worth remembering those chips had a lot of engineering effort put in them outside of manufacturing process) but it should permit chips of somewhat decent performance. It's a very generous thing!

[0]: https://en.wikipedia.org/wiki/130_nm_process

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