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ULX3S: Hackable FPGA that runs Linux on RISC-V

ulx3s.github.io

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Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#21

Post by mhh__ »

bloopernova wrote: post #6

Layman question: how many years before we get RISC-V desktops or Raspberry Pi like computers?

Desktops, perhaps never - 10 years? Alibaba seem to be funding some R&D in this direction, but I'm not too familiar (and I can't speak Chinese). It's certainly possible, but desktop processors aren't simple in any way. Regardless of absolute technical excellence, RISC-V only has to be better than ARM (in both specification and implementation, and cost, of course) which will be a moving target as RISC-V improves.

Single Board Computers - https://www.sifive.com/boards/hifive-unleashed this seems to fit the bill. However, they don't seem to be selling those yet - the development kit for that particular CPU seems to be an FPGA soft-core.

I am currently working on an open-hardware project that requires a fair amount of grunt (or FPGA); in an effort to keep is open I was looking into RISC-V processor's. You can actually buy RISC-V hardware today as a guy on the street (i.e. Digikey etc.) but the offerings I could find were generally fast microcontrollers rather than general purpose processors.

If RISC-V is to be adopted it's probably more of a question of engineering knowledge and training than solely hardware: One of the chips I found in my search above is an interesting Chinese system on module that has a RISC-V at 400MHz, Wi-Fi, and a hardware NN coprocessor - it's a cool chip but even in Chinese the documentation is unusable and awful.

If a big western company like ST or Cypress etc. picks up RISC-V and starts making it easy and safe to actually use (for example, the section of the manual for the serial peripherals on most NXP microcontrollers is longer than all the documentation I could find for the aforementioned SoM).

Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#23

Post by OJFord »

pmiller2 wrote: post #5
dmos62 wrote: post #3

Earlier quoted context omitted.

I initially misunderstood this headline to mean the opposite: I took "drops" to mean "introduces", which is the opposite of the intended meaning -- "withdraws". Not sure where I got this non-mainstream meaning of "to drop".

People do talk about “dropping” an album to indicate it’s being released. Your confusion is somewhat understandable. English is hard. :(

You might enjoy:

https://en.m.wikipedia.org/wiki/Auto-antonym

Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#24

Post by haberman »

Is there any published rationale for the RISC-V instruction encoding?

A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables.

But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/master/src/commo...

In particular:

    - The bit patterns allocated to the simplest instructions
      (eg. rv32i) seem random. Why not allocate starting from zero
      to allow dense jump tables?
    - I can't make any sense of the groupings. A bunch of instructions
      have 0b1100011 in the lowest bits, do these instructions have
      something in common?
I assume there is some rhyme and reason to all this? Where is this explained?

Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#26

Post by dahfizz »

haberman wrote: post #24

Is there any published rationale for the RISC-V instruction encoding? A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables. But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/…

I agree. I had to write a dissembler for RISC-V in college and it was surprisingly annoying.

Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#27

Post by OJFord »

mhh__ wrote: post #21
bloopernova wrote: post #6

Layman question: how many years before we get RISC-V desktops or Raspberry Pi like computers?

Desktops, perhaps never - 10 years? Alibaba seem to be funding some R&D in this direction, but I'm not too familiar (and I can't speak Chinese). It's certainly possible, but desktop processors aren't simple in any way. Regardless of absolute technical excellence, RISC-V only has to be better than ARM (in both specification and implementation, and cost, of course) which will be a moving target as RISC-V improves. Sing…

> for example, the section of the manual for the serial peripherals on most NXP microcontrollers is longer than all the documentation I could find for the aforementioned SoM

In Chinese though? Or did you compare long English to short Chinese?

Because, I don't speak (or read) it either, but compared to English it's extremely information sense: its characters are closer to whole words than to Latin letters. In fact if you think of it also being like German, with Longerwordbuiltfromothers, they are, and L... would be just a few characters at most.

Not that that makes Chinese documentation any more helpful to us non-speakers, though.

Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#28

Post by r1sc5away »

haberman wrote: post #24

Is there any published rationale for the RISC-V instruction encoding? A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables. But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/…

I'm not sure about publications that try to answer "why RISC-V?", but the specification often describes the rationales behind many of these kinds of decisions.

The bit patterns are often designed to make it easier to write efficient hardware designs to implement them. For example, if an instruction encodes an "immediate" value, the most significant bit of the instruction will always hold that value's sign-extension bit. And if you compare the immediate values in I-/S-/B-/J-type instructions, you can see that bits [5:10] are always in the same place. It's not exactly intuitive, but there is some rhyme and reason.

In the base instruction set, the 0b1100011 opcode encodes a set of conditional branch instructions. They perform relative jumps if rs1 == rs2, or if rs1 https://riscv.org/specifications/isa-spec-pdf/

Take a look at the "RV32/64G Instruction Set Listings" table to get a feel for the encodings.

Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#29

Post by mhh__ »

OJFord wrote: post #27
mhh__ wrote: post #21

Earlier quoted context omitted.

Desktops, perhaps never - 10 years? Alibaba seem to be funding some R&D in this direction, but I'm not too familiar (and I can't speak Chinese). It's certainly possible, but desktop processors aren't simple in any way. Regardless of absolute technical excellence, RISC-V only has to be better than ARM (in both specification and implementation, and cost, of course) which will be a moving target as RISC-V improves. Sing…

> for example, the section of the manual for the serial peripherals on most NXP microcontrollers is longer than all the documentation I could find for the aforementioned SoM In Chinese though? Or did you compare long English to short Chinese? Because, I don't speak (or read) it either, but compared to English it's extremely information sense: its characters are closer to whole words than to Latin letters. In fact if…

> In Chinese though? Or did you compare long English to short Chinese?

I did some google translate-ing and had some help from my token Chinese friend. I might have missed it but the document had the same structure in English and Chinese. In short, you could probably work it out by reading the rtos they distribute for you to use and there is a little documentation of the actual peripherals but it is absolutely bare bones. And that's (what we would call) application notes, the actual datasheet is pretty much just some marketing BS and a PCB footprint (not that they actually provide any symbols - sometimes even the big chip makers don't bother which is quite annoying if you're stuck using anything other than Altium)

Re: ULX3S: Hackable FPGA that runs Linux on RISC-V

#30

Post by dahfizz »

bloopernova wrote: post #6

Layman question: how many years before we get RISC-V desktops or Raspberry Pi like computers?

Others have pointed out economic problems with producing hardware, which is fair, but another big issue is standardization.

There is no RISC-V equivalent of BIOS / UEFI, multiboot, etc. We take it for granted that all motherboards and all bootable drives 'just work'. That kind of consistency is important for consumer desktop PCs (less so for rasberry-pi type machines).

This is being worked on, and I think a stable specifications are not too far away. I imagine it will still take firmware developers a long time to create motherboards that fit the spec, considering they are starting from scratch. Here is a recent presentation about the state of booting RISC-V[1].

[1]https://content.riscv.org/wp-content/uploads/2019/12/Summit_...

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