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VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

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Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#21

Post by anonymousDan »

londons_explore wrote: post #15
rkagerer wrote: post #12

I'm disappointed today's general purpose CPU's and microcontrollers don't come with some integrated FPGA space, similar to how you have SRAM and other peripherals. Intel talked about it a few years back [1] but I'm not sure anything materialized. The closest I've seen in popular chips is a few gates worth of programmable logic. Are there any hidden gems I've missed out on? [1] https://www.nextplatform.com/2018/05/24/…

With the transition of compute from performance focussed to performance per watt focussed (due to cooling usually being the limiting factor), the niche for the FPGA has almost vanished. There are very very very few compute tasks where an FPGA solves a problem with better performance per watt than both a CPU and a GPU. I would bet that emulating a RISC-V program on x64 is far more power efficient than running a RISC-V…

I thought FPGAs were more power efficient than GPUs for many ML applications for example (CNNs aside)?

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#22

Post by acrossthepond10 »

FPGA Noob here. I have 2 questions about FPGA's that I'm hoping someone here can help me out with:

1. For the FPGAs i've looked at, you seem to have to initially configure them before being able to run your programs on them, kind of like EEPROM. I feel it would be much more interesting from a reconfigurable computing perspective if the devices were able to programatically re-configure on the fly as easily as it is to read and write to DRAM or Flash Memory. So what are the barriers that prevent the hardware from being able to do this?

2. Its exciting to see projects like Symbiflow making great progress, but after reading some expert opinions[1] it seems like an extremely difficult challenge to attempt to reverse engineer hardware from commercial FPGA vendors who wish to keep their designs closed in order to protect their IP and compete. So my question is wouldn't it be a more feasible goal to construct fully open FPGA platform from scratch, just like RISC-V is doing with CPUs? What would the obstacles be here?

Thanks!

[1] https://www.reddit.com/r/FPGA/comments/a5pzs5/prediction_ope...

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#23

Post by tverbeure »

acrossthepond10 wrote: post #22

FPGA Noob here. I have 2 questions about FPGA's that I'm hoping someone here can help me out with: 1. For the FPGAs i've looked at, you seem to have to initially configure them before being able to run your programs on them, kind of like EEPROM. I feel it would be much more interesting from a reconfigurable computing perspective if the devices were able to programatically re-configure on the fly as easily as it is to…

1. Most higher capacity FPGA have a features called "partial reconfiguration" where you can reload a part of the FPGA with a new bitstream. This new part can usually come from anywhere (PCIe, SPI, ...)

2. RISC-V is a ISA. It's not an implementation. You can implemented it on FPGA or ASIC. When you implement a RISC-V on an FPGA, it will cost you between $2 and maximum a few $1000 in silicon. FPGA technology itself is something that can only reasonably be implemented in an ASIC. The initial cost of an ASIC can go anywhere from $100K (on a very old process) to multiple millions.

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#25

Post by tverbeure »

eebynight wrote: post #16

The fact that it fits in the 35T version with room to spare is pretty huge, especially since certain packages of the 35T start as low as $35 for a single chip, no MOQ. I could see myself dropping one of these on a homemade project if I ever spend the time making a reliable reflow oven...

If you're happy that it fits in a 35T, you'll be ecstatic to learn that a single VexRiscv fits comfortably in a Cyclone II EP2C5 FPGA. :-)

It's hard to find an FPGA that's too small to fit one.

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#26

Post by mhh__ »

acrossthepond10 wrote: post #22

FPGA Noob here. I have 2 questions about FPGA's that I'm hoping someone here can help me out with: 1. For the FPGAs i've looked at, you seem to have to initially configure them before being able to run your programs on them, kind of like EEPROM. I feel it would be much more interesting from a reconfigurable computing perspective if the devices were able to programatically re-configure on the fly as easily as it is to…

1. I'm not sure what you mean but remember that FPGAs don't run programs as per se (HDL gets compiled to logic, not instructions). The bitstream can be modified, it just gets loaded from some flash. I'm not sure where it's done, but it's possible.

2. The obstacles are billions and billions of R&D (and you'd need similar amounts to get a fab pick up the phone too). Reverse engineering the bitstream is also difficult because of this - Symbiflow (i.e. Trellis etc.) have got the bulk of the bitstream done (apart from specialized blocks like those for DSP), but you need to have good algorithms to decide what to do with that bitstream e.g. a fully open source flow requires intricate timing analysis.

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#27

Post by londons_explore »

monocasa wrote: post #17
londons_explore wrote: post #15

Earlier quoted context omitted.

With the transition of compute from performance focussed to performance per watt focussed (due to cooling usually being the limiting factor), the niche for the FPGA has almost vanished. There are very very very few compute tasks where an FPGA solves a problem with better performance per watt than both a CPU and a GPU. I would bet that emulating a RISC-V program on x64 is far more power efficient than running a RISC-V…

There's a lot of use cases today where perf per watt doesn't matter.

Name some... Any task where perf per dollar matters also boils down to perf per watt, since watts cost dollars...

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#28

Post by mhh__ »

magicalhippo wrote: post #20
rkagerer wrote: post #12

I'm disappointed today's general purpose CPU's and microcontrollers don't come with some integrated FPGA space, similar to how you have SRAM and other peripherals. Intel talked about it a few years back [1] but I'm not sure anything materialized. The closest I've seen in popular chips is a few gates worth of programmable logic. Are there any hidden gems I've missed out on? [1] https://www.nextplatform.com/2018/05/24/…

Well Xilinx has the Zynq-7000 SoC[1], featuring an ARM Cortex-A9 CPU along with a potentially quite large FPGA. Not exactly cheap though, at least in small quantities[2] [1]: https://www.xilinx.com/products/silicon-devices/soc/zynq-700... [2]: https://www.digikey.com/products/en/integrated-circuits-ics/...

Intel has the Cyclone V range.

Also, I've never done it myself but I've read that digikey prices are almost never the actual price for FPGAs even in relatively small quantities (haggling with avnet).

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#29

Post by londons_explore »

anonymousDan wrote: post #21
londons_explore wrote: post #15

Earlier quoted context omitted.

With the transition of compute from performance focussed to performance per watt focussed (due to cooling usually being the limiting factor), the niche for the FPGA has almost vanished. There are very very very few compute tasks where an FPGA solves a problem with better performance per watt than both a CPU and a GPU. I would bet that emulating a RISC-V program on x64 is far more power efficient than running a RISC-V…

I thought FPGAs were more power efficient than GPUs for many ML applications for example (CNNs aside)?

For unusual ML architectures, like 1 bit precision, that might be true.

For anything using floating point maths, it isn't true.

Re: VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA

#30

Post by monocasa »

londons_explore wrote: post #27
monocasa wrote: post #17

Earlier quoted context omitted.

There's a lot of use cases today where perf per watt doesn't matter.

Name some... Any task where perf per dollar matters also boils down to perf per watt, since watts cost dollars...

Say, robotics where the difference between an FPGA and something else is way overshadowed by the motors.

Or really basically anywhere that has you interacting with the real world directly connected to your compute, and not just compute off in a datacenter.

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