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Earlier quoted context omitted.
With the right systems in place, you can be protected from physical compromise. For example, if my credit card is stolen, I call visa and I'm fine.
And who do you think foots the bill? You might not pay it in one lump sum, but I’m pretty sure you still pay it.
It would seem very easy to put a pair of fets in such a way they detected sudden voltage changes (via their gate capacitance). That could then be used as an input to a circuit which ensured the chip is properly reset by asserting the reset line for at least 1 clock cycle.
This should probably be paired with brown-out detection, although that's power hungry, so I can see why people might not want it.
This wouldn't only have security benefits - lots of electronic designs might be accidentally glitching their microcontrollers due to poor design of other circuits, and having the chip reset in a predictable way is much better than undefined behaviour.
Earlier quoted context omitted.
And who do you think foots the bill? You might not pay it in one lump sum, but I’m pretty sure you still pay it.
People who lost 100% of their coins are probably wishing they had the option to buy some kind of insurance. But no, be your own bank. (Wait, don't real banks also have insurance?)
Nothing in this flaw is a surprise considering Trezor does not even use a secure element (unlike Ledger).
It’s surprising considering how cheap SIM card chips are. It’s not hard to do secure elements these days, at least at scale.
Some lucky people will be able to restore lost crypto.
https://www.wired.com/story/i-forgot-my-pin-an-epic-tale-of-...
Luckily he hadn't updated the firmware so the vulnerability wasn't patched on his device, but despite that, it took a long time and was not easy. But like this newer vulnerability, it would almost be impossible if he had also used a strong passphrase, as Trezor recommends.
Trezor is designed to protect against remote/logical attacks (including a compromised host). It isn't really hardware protected in any meaningful way against local access. This lets users inspect/validate their own hardware better, though. The issue is most users (reasonably, IMO) assume physical protection for their hardware wallets, at least against someone getting temporary access and without insane levels of reso…
I would definitely pick Coldcard over Ledger though.
Coldcard is open source and open hardware to a much greater extent, while still using secure element for secret storage and PIN counter. It also offers advanced security features like proper multisig support, airgaped operation, roll-your-dice entropy input, etc.
In particular this statement:
> That being said, we were surprised by Ledger’s announcement of this issue, especially after being explicitly asked by Ledger not to publicize the issue, due to possible implications for the whole microchip industry, beyond hardware wallets, such as the medical and automotive industries.
As I understand they are using a standard STM32 chip for these wallets, and relying on it's basic protection. Companies make real processes designed for securely storing data, why aren't they using them? Instead they are suggesting that there is no alternative and everyone is vulnerable to this style of attack.
Edit: I missed some of the backstory. They don't mention that option as their competitor (who found the security issues) already uses a secure element, like a sane person.
[1] - https://blog.trezor.io/our-response-to-ledgers-mitbitcoinexp...
Why don't all silicon chips have glitch and overvoltage detection? It would seem very easy to put a pair of fets in such a way they detected sudden voltage changes (via their gate capacitance). That could then be used as an input to a circuit which ensured the chip is properly reset by asserting the reset line for at least 1 clock cycle. This should probably be paired with brown-out detection, although that's power h…
Why don't all silicon chips have glitch and overvoltage detection? It would seem very easy to put a pair of fets in such a way they detected sudden voltage changes (via their gate capacitance). That could then be used as an input to a circuit which ensured the chip is properly reset by asserting the reset line for at least 1 clock cycle. This should probably be paired with brown-out detection, although that's power h…