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Reviewing Bad Schematics as EE Interview Tactic

cushychicken.github.io

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Re: Reviewing Bad Schematics as EE Interview Tactic

#21
post #12

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

I'm an EE. My first job out of university had a pretty good whiteboard interview (I know - we're not supposed to say good things about whiteboard interviews on HN). I thought the process was pretty straightforward. The first exchange went something like this: Interviewer: "Can you draw me the schematic symbol for an LED?" Me: Draws LED schematic symbol. Interviewer: "What would you say the forward voltage is on that…

I did 0.5 EE degree in the best Uni in my country with very good grades and my level of insight wrt how ICs work borderlines a Golden Retriever.

But I'm modestly good at math and the EE classes were essentially an elaborate sequence of math riddles (complex functions? Fourier? I'm great at that), superficially excused as representing some "circuit".

Re: Reviewing Bad Schematics as EE Interview Tactic

#22
Here are some of my RF specific interview questions. Spend no more than 1 minute on each.

Power Amplifiers

Q: Where do GaAs/GaN FETs DC gate currents originate, and why are they positive and negative?

Q: How would you temperature compensate the transistor DC bias.

Q: What is AM-AM and AM-PM distortion and how would you measure it?

Q: Give an example of a “memory effect”.

Passive RF/Microwave Circuits

Q: How would you measure unloaded Q of a resonator?

Q: What is self-resonant frequency of a component (i.e. chip L or C) and when is it useful.

Q: Why does a stripline coupler typically perform better than microstrip?

Q: What’s the characteristic impedance and electrical length for the lines in a 2-way Wilkinson splitter.

Q: Where does the current flow on a microstrip line and its return path?

Test and Measurement

Q: What’s the difference between RBW and VBW on a spectrum analyzer?

Q: When is a sliding load used in VNA calibration and how does it work?

Q: What does noise marker mode do on a spectrum analyzer?

Q: How would you measure a SMT part at several GHz with proper reference planes?

Q: What’s a quick way to tell if your spectrum analyzer is contributing to IMD3.

Digital Comms

Q: Why are RRC filters used so frequently?

Q: Describe the flow of PSK receiver?

Q: What is an Error Vector Magnitude (EVM) measurement?

Q: What effect does clock jitter have on an ADC or DAC.

Q: Would a class C amplifier work better with OFDM or FSK?

Antennas

Q: What typically limits the bandwidth on a single frequency patch antenna?

Q: What’s common mode radiation on a coax (to antenna) transition and what are a couple of ways to minimize it.

Q: What happens to an antenna’s input impedance and directivity when you move it very close to a “ground plane”.

Q: What’s an IFA or PIFA antenna and how does it relate to a monopole; why are they so common in compact devices.

Q: Given a VNA and two linearly polarized horn antennas with known gain, how would you measure the gain of a circularly polarized antenna?

RF Front Ends

Q: What are the typical blocks in a superhet receiver (or down conversion chain)?

Q: What typically determines diode mixer linearity?

Q: What’s IMD?

Q: What’s more important in LNA; noise or impedance match?

Q: What’s cross-modulation?

Synths and Oscillators

Q: What are the advantages and dis-advantages of a Frac-N over an Integer-N synth?

Q: What specs would you look for in a linear regulator to isolate a synth analog section from a switching supply?

Q: Given you don’t care about settling time, how would you set loop filter bandwidth to achieve best noise performance?

Q: Given you don’t care about settling time, how would you set loop filter bandwidth to achieve best noise performance?

Q: What do synth ICs have charge pump trim settings (i.e. upper and lower different gains)?

Connectors and Waveguides

Q: What is skin effect?

Q: What is the torque specification for a 3.5mm connector?

Q: Why is nickel used in plating processes? What effect does it have on RF?

Q: What’s the highest frequency that an SMA connector can be used for TEM propagation? What happens above that?

Q: If you needed to slice a rectangular waveguide in half, would you slice down the broad wall or the narrow wall? Why?

Simulation

Q: Why would use you use 2D thick metal (or 3D EM) on edge coupled lines? Is there a rule of thumb?

Q: Would you use harmonic balance or transient simulation (or both) to model a simple diode detector?

Q: What are some quick methods to determine if your EM simulation is plausible?

Q: Given microstrip element models, would you model a short, wide line as a line with two steps, or a cross with two long stubs; the layout is identical.

Q: What type of EM simulator (2D or 3D, infinite or finite boundary, gridded or gridless, time or frequency domain) would you use for: patch antenna, planar filter, horn antenna, cavity filter. Why?

Re: Reviewing Bad Schematics as EE Interview Tactic

#23
Things that come to mind for bad schematic review:

* Linear voltage regulator with high input voltage powering an obviously very power hungry load.

* No ESD protection/current limiting for sensitive pins exposed to outside world.

* Tantalum capacitors with very narrow voltage rating margin

Another tactic I like (something similar is mentioned in sibling comment): a small design problem representative of real life task.

For generic EE position I like the following: "Suppose there is a project using this microcontroller. Project requires this micro to power an externally connected solenoid with this specification."

I find this reveals a lot of the seniority/thought process of the candidate: what (if any) questions candidate is asking to better understand the problem ("Do I need to consider output short circuit? What are the cost/size constraints? Don't we need a internal/external feedback?"), what is their process of component selection (if that is required in job description) and the suitability of this process for the needs of particular company.

Now, if only I could come up with similar strategies for software positions...

Re: Reviewing Bad Schematics as EE Interview Tactic

#24
post #14

Earlier quoted context omitted.

>It seems strange that the author has not met a single one that understands that concept since it is quite basic. That's exactly what everyone says when candidates fail FizzBuzz. The best explanation I know is that good candidates get hired quickly, so at any given moment, the candidate pool is dominated by people who keep failing questions like this.

He is saying that all juniors fail EE-FizzBuzz, which makes me question his interviewing skills.

And a lot of interviewers report that all juniors fail FizzBuzz.

Re: Reviewing Bad Schematics as EE Interview Tactic

#26
post #4

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

Seems like it says more about the writer's hiring pool. I can't think of one junior EE I've interacted with who couldn't have told you what decoupling caps were for. Sizing them correctly (instead of just sprinkling the 0.1uF magic fairy dust on your board) might be another matter but I've yet to see someone fail to grasp the purpose.

There's also a difference between "can tell you what decoupling caps are for" and "when given a circuit will call them out as missing", especially in an interview situation. (Parallels probably apply to software interviews: under stress it's easier for many to answer "define X" than to identify how/if to apply X when not prompted for it)

Re: Reviewing Bad Schematics as EE Interview Tactic

#28
post #12

Earlier quoted context omitted.

I'm an EE. My first job out of university had a pretty good whiteboard interview (I know - we're not supposed to say good things about whiteboard interviews on HN). I thought the process was pretty straightforward. The first exchange went something like this: Interviewer: "Can you draw me the schematic symbol for an LED?" Me: Draws LED schematic symbol. Interviewer: "What would you say the forward voltage is on that…

"Universities these days do not seem to successfully evaluate deep understanding" If you (as Uni) try and do that, you'd immediately find your quota of those who have finished a degree to plummet. At our university we had basically only TWO courses that required you to "understand" to pass them and not just mindlessly puke out formulas and insert values. These were theoretical electrodynamics and integrated analog ci…

> If you (as Uni) try and do that, you'd immediately find your quota of those who have finished a degree to plummet.

Indeed: as a teacher, I have had the experience that there's pressure to pass underachieving students in the elementary courses (we don't want to scare everyone off by flunking them out of their first courses!) and then there's pressure to pass underachieving students in the advanced courses (it's not fair to pass them to this point, and then suddenly hold them to higher expectations!—or even, directly, "if we don't pass them then they won't be able to graduate").

Re: Reviewing Bad Schematics as EE Interview Tactic

#29
Sorry but this is probably terrible. Without knowing the part datasheet this interview isn’t going to tell you much. I think it’s much better to focus on signals/systems plus some circuit level problems that focus on the basics; open drain outputs, op-amps, RC/RLC circuits, transmission lines etc...

Re: Reviewing Bad Schematics as EE Interview Tactic

#30
I’ve tried (and abandoned) a similar question suite for Security SWEs. Giving people sample code riddled with security flaws and asking them to explain what was wrong.

I found it difficult in the security domain since so much of it is context dependent (what’s the interface? Is this code in the kernel? Are you concerned about speculative side channels?). I also found it difficult to calibrate.

There’s probably a good question space in there if I were to spend time testing the questions more, but there are enough other questions in the neighborhood that I’ve moved on.

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