SiFive Announces First RISC-V OoO CPU Core • Hacker News Board

Re: SiFive Announces First RISC-V OoO CPU Core

#11

Post by audunw » Wed, Oct 30, 2019, 4:02 PM UTC

baybal2 wrote: post #8

> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…

The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs. If I remember correctly, that's one of the reasons everyone jumped ship from OpenRISC to RISC-V (the big mistake in OpenRISC being branch delay slots I believe)

It might also help starting from scratch.

I'm also not convinced it's entirely an apples-to-apples comparison. ARM might support more complex instructions that their core don't, and the ARM core might have features like TrustZone.

Re: SiFive Announces First RISC-V OoO CPU Core

#12

Post by monocasa » Wed, Oct 30, 2019, 4:06 PM UTC

gnode wrote: post #9

cfallin wrote: post #6

Earlier quoted context omitted.

"IP core" can mean "soft IP", which is just RTL, or "hard IP", which is a full layout (set of mask layers), ready to put on silicon. I haven't read the SiFive announcement closely, but if they're quoting area/frequency/power numbers, it would most likely be the latter.

Interestingly, although all the RTL for the SiFive Freedom platform is in the SiFive's GitHub repository, and they've produced chips and boards (with public schematics and BOM), the hard IP doesn't appear to be public. I wonder if this is because the hard IP is specific to the fabs' trade secret tooling, and so subject to their NDAs, making it impossible to distribute publicly.

You're on point with the second paragraph. I only know of one chip fab that has it's design rules public, and they're an open source fab running out of HKUST that'll give you about Arduino level gate counts.

Re: SiFive Announces First RISC-V OoO CPU Core

#13

Post by kick » Wed, Oct 30, 2019, 4:07 PM UTC

baybal2 wrote: post #8

> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…

SiFive was founded by most of the initial RISC-V designers, and is easily one of the companies with the most raw talent in the field right now.

Re: SiFive Announces First RISC-V OoO CPU Core

#14

Post by bcheung » Wed, Oct 30, 2019, 4:10 PM UTC

I wasn't sure what OoO stood for and since they never mentioned it in the article I had to look it up. For anyone else who is asking the same question.

OoO = out of order execution

Re: SiFive Announces First RISC-V OoO CPU Core

#15

Post by cesarb » Wed, Oct 30, 2019, 4:22 PM UTC

audunw wrote: post #11

baybal2 wrote: post #8

> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…

The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs. If I remember correctly, that's one of the reasons everyone jumped ship from OpenRISC to RISC-V (the big mistake in OpenRISC being branch delay slots I believe) It might also help starting from scratch. I'm also not convinced it's entirely an apples-to-apples comparison. ARM might support more complex instr…

> The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs.

ARM's 64-bit architecture (AArch64) was also made with similar hindsight, so that's probably not the whole reason.

Re: SiFive Announces First RISC-V OoO CPU Core

#16

Post by rrss » Wed, Oct 30, 2019, 4:35 PM UTC

baybal2 wrote: post #8

> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…

7nm instead of 16nm probably helps a lot.

Re: SiFive Announces First RISC-V OoO CPU Core

#17

Post by SlowRobotAhead » Wed, Oct 30, 2019, 4:45 PM UTC

bcheung wrote: post #14

I wasn't sure what OoO stood for and since they never mentioned it in the article I had to look it up. For anyone else who is asking the same question. OoO = out of order execution

I’m right there with you!

I’ve been doing embedded hardware and CE work for 15 years non-stop, and had no idea what OoO meant.

Kept thinking “on a”. As in SoC or PoC.

Re: SiFive Announces First RISC-V OoO CPU Core

#18

Post by BookPage » Wed, Oct 30, 2019, 4:49 PM UTC

bcheung wrote: post #14

I wasn't sure what OoO stood for and since they never mentioned it in the article I had to look it up. For anyone else who is asking the same question. OoO = out of order execution

It’s actually mentioned in a header after the third paragraph in the article...

Re: SiFive Announces First RISC-V OoO CPU Core

#19

Post by wolf550e » Wed, Oct 30, 2019, 4:52 PM UTC

monocasa wrote: post #12

gnode wrote: post #9

Earlier quoted context omitted.

Interestingly, although all the RTL for the SiFive Freedom platform is in the SiFive's GitHub repository, and they've produced chips and boards (with public schematics and BOM), the hard IP doesn't appear to be public. I wonder if this is because the hard IP is specific to the fabs' trade secret tooling, and so subject to their NDAs, making it impossible to distribute publicly.

You're on point with the second paragraph. I only know of one chip fab that has it's design rules public, and they're an open source fab running out of HKUST that'll give you about Arduino level gate counts.

Why can't a fab with something like 28nm use public design rules? I guess there aren't valuable trade secrets still in a process that old. But some chips can usably be made on such a process.

Re: SiFive Announces First RISC-V OoO CPU Core

#20

Post by Sanzig » Wed, Oct 30, 2019, 5:00 PM UTC

wolf550e wrote: post #19

monocasa wrote: post #12

Earlier quoted context omitted.

You're on point with the second paragraph. I only know of one chip fab that has it's design rules public, and they're an open source fab running out of HKUST that'll give you about Arduino level gate counts.

Why can't a fab with something like 28nm use public design rules? I guess there aren't valuable trade secrets still in a process that old. But some chips can usably be made on such a process.

There's a lot of mixed-signal specialty ASICs at the 350 nm and 180 nm nodes. As long as you don't need the density, it's a great option. Masks are relatively cheap and the processes are dialed in extremely well at this point. Just because the tech is 20-30 years old doesn't mean it's not useful.