SiFive Announces First RISC-V OoO CPU Core
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SiFive Announces First RISC-V OoO CPU Core
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Re: SiFive Announces First RISC-V OoO CPU Core
#2"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.
Re: SiFive Announces First RISC-V OoO CPU Core
#3> A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm.
Pretty cool that these chips are approaching performance parity so quickly.
Re: SiFive Announces First RISC-V OoO CPU Core
#4"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.
IP cores are sometimes deployed on FPGAs though, so that can be a working chip (depending on definitions).
Re: SiFive Announces First RISC-V OoO CPU Core
#5"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.
I think this may be more than a register-level transfer abstraction. The slides make claims about die area and frequency, and show a layout.
SiFive offer IP but also produce SoCs (presumably with TSMC, SMIC, and GlobalFoundries, who are listed as partners).
Re: SiFive Announces First RISC-V OoO CPU Core
#6"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.
I think this may be more than a register-level transfer abstraction. The slides make claims about die area and frequency, and show a layout. SiFive offer IP but also produce SoCs (presumably with TSMC, SMIC, and GlobalFoundries, who are listed as partners).
"IP core" can mean "soft IP", which is just RTL, or "hard IP", which is a full layout (set of mask layers), ready to put on silicon. I haven't read the SiFive announcement closely, but if they're quoting area/frequency/power numbers, it would most likely be the latter.
Re: SiFive Announces First RISC-V OoO CPU Core
#7"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.
I think this may be more than a register-level transfer abstraction. The slides make claims about die area and frequency, and show a layout. SiFive offer IP but also produce SoCs (presumably with TSMC, SMIC, and GlobalFoundries, who are listed as partners).
When you are selling IP like this you would need to do your own physical design due diligence, even if the deliverable is just some Verilog code.
Re: SiFive Announces First RISC-V OoO CPU Core
#8> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area.
This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio.
Where does SiFive get such an expertise in size optimisation?
Re: SiFive Announces First RISC-V OoO CPU Core
#9Earlier quoted context omitted.
I think this may be more than a register-level transfer abstraction. The slides make claims about die area and frequency, and show a layout. SiFive offer IP but also produce SoCs (presumably with TSMC, SMIC, and GlobalFoundries, who are listed as partners).
"IP core" can mean "soft IP", which is just RTL, or "hard IP", which is a full layout (set of mask layers), ready to put on silicon. I haven't read the SiFive announcement closely, but if they're quoting area/frequency/power numbers, it would most likely be the latter.
Interestingly, although all the RTL for the SiFive Freedom platform is in the SiFive's GitHub repository, and they've produced chips and boards (with public schematics and BOM), the hard IP doesn't appear to be public.
I wonder if this is because the hard IP is specific to the fabs' trade secret tooling, and so subject to their NDAs, making it impossible to distribute publicly.
Re: SiFive Announces First RISC-V OoO CPU Core
#10> SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio. Where does SiF…
I wonder if that's comparing the non-vector U84 against the A72 with Neon.