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TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

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Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#71

Post by thechao »

garmaine wrote: post #30
sanxiyn wrote: post #20

Earlier quoted context omitted.

I think an important difference is that EUV exists now.

That’s how you make the chip. I’m not doubting that you can get manufacturing smaller, for a while[0]. But will it still work? You’re getting into the domain where electrons start tunneling across transistors and such. There is a wall that we will hit where lithography can take us no further—we’ll need atomic precision to break through that wall. It’s just a question of where that wall is... [0]: Higher frequency UV…

Transistors at 7 & 5 are nowhere close to having serious “quantum” issues—that regime is thousands of times smaller than current gate design. Remember that the “size” is a marketing term that really relates most closely to “effective” wire pitch & gate density with respect to processes in the hundreds-of-nanometer scale. The absolute smallest functioning design I’ve read about is IBM’s 7-atom gate. That gate is something like 100thousand times smaller (volumetrically) than current production.

Also, current HW design is really inefficient. Think about all the crud between some front-end developer and the server powering the webpage on the backend, vs a ‘native’ app. That’s a good analogy to current HW design and real total-badass low level HW design.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#73

Post by londons_explore »

In today's world of geopolitics, restricting access to decent silicon processes can have a massive knock on on other industries.

If Taiwan/China have better silicon manufacturing capabilities now, they can restrict export of those chips, to effectively capture the phone/server markets too...

Could be a big part in the nail in the coffin for USA tech dominance.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#74

Post by rbanffy »

ww520 wrote: post #59
opencl wrote: post #48

Earlier quoted context omitted.

Sure TSMC is more focused but Intel has dramatically greater resources. Their R&D budget is ~5x TSMC's and ~10x AMD's. You have to be pretty badly distracted to fail to produce superior products with such an enormous budget advantage. Intel technically accepts outside fab contracts but they haven't had any customers since they bought out Altera, their previous only customer. [1] https://ycharts.com/companies/INTC/r_a…

Intel's budget is not just for chip fabrication, they have a very wide array of product areas. Chip foundry is very cost intensive, in the range of 10's billions. I'm not surprised TSMC spends way more on fabrication than Intel does.

According to the numbers of the post above, if they allocate more than 20% of their R&D budget to process improvements and more than 10% to their architecture improvements, they match or exceed their two rivals, leaving 70% to be allocated to other tracks, which I find rather excessive all things considered.

I remember a comment I made a long time ago, in the beginning of the Browser Wars: Microsoft had more people assigned to design their icons than NetScape had employees. NetScape's fate was sealed from the get go and their resilience was commendable.

And yet, in the end, Microsoft still lost that war.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#75

Post by kkmx »

dumbfoundded wrote: post #67
wmf wrote: post #16

Earlier quoted context omitted.

From the same site: https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells... Scroll down near the bottom.

To summarize the article: the density at which Intel can pack the transistors on a chip is high enough even with a larger transistor size, still means Intel has more transistors in the same chip size. The advantage of the 7nm TSMC transistor is that they are faster and more power-efficient.

No that's not a correct summary either. The part about faster and more power-efficient is incorrect.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#76

Post by 6nf »

londons_explore wrote: post #39
umvi wrote: post #34

Earlier quoted context omitted.

Well, the diameter of a silicon atom is 0.2nm, so I would guess it's at least that with silicon-based computers.

Not necessaraly. The node size represents the equivalent 'gate' size of a standard transistor with similar performance characteristics. By using better transistor designs, you can make the effective gate size much smaller than the actual gate size.

You can't make features smaller than one atom though, and silicon atoms in a crystal matrix are about 0.5nm apart.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#77

Post by bitL »

AFascistWorld wrote: post #66
bitL wrote: post #58

Earlier quoted context omitted.

I would vote for Lisa to be the CEO of the year. It's also fun to know she is a relative of NVidia boss that once worked at AMD and they both are from Taiwan, home of TSMC and who knows if they have family inside as well...

No she's not his relative.

"It is worth mentioning that another Taiwanese semiconductor elite, Nvidia founder Huang Renxun (Jensen Huang) also came from Tainan, and has a relative relationship with Su Zifeng (Lisa Su). Su Zifeng’s grandfather and Huang Renxun’s mother are brothers and sisters"

https://old.reddit.com/r/nvidia/comments/8pdxo7/nvidias_ceo_...

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#78

Post by sct202 »

londons_explore wrote: post #73

In today's world of geopolitics, restricting access to decent silicon processes can have a massive knock on on other industries. If Taiwan/China have better silicon manufacturing capabilities now, they can restrict export of those chips, to effectively capture the phone/server markets too... Could be a big part in the nail in the coffin for USA tech dominance.

Uh, why are you lumping Taiwan in with China? They're 2 separate governing entities that aren't particularly friendly, and have missiles pointed at each other.

Re: TSMC Talks 7nm, 5nm, Yield, and Next-Gen 5G and HPC Packaging

#79

Post by ivalm »

sixplusone wrote: post #50
ivalm wrote: post #26

Earlier quoted context omitted.

There is a lot of density that can be increased. The node size doesn't represent transistor size, not even the gate size.

wouldn't that become a heat dissipation issue?

If you need to move charge then you get nasty joule heating, but if you only move spin density then this causes almost no heating (that's the promise of spintronics)
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