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PCI Express on the Raspberry Pi 4

mloduchowski.com

61–70 of 166 posts

Re: PCI Express on the Raspberry Pi 4

#61
post #56

Earlier quoted context omitted.

You could just use an USB device for higher throughput. The Sandisk Extreme Go, for example, is basically a small SSD in a USB drive form-factor.

If I’m reading it right, don’t you give up USB to get this PCIe access?

Yes, that's my point.

Re: PCI Express on the Raspberry Pi 4

#63
post #43

Why not, but I will wait for a classic ATX ARM motherboard instead. It should happen this year.

Is Mini-ITX for $550 acceptable? https://www.solid-run.com/nxp-lx2160a-family/honeycomb-works... 16 core A72 CPU, up to 64GB RAM, PICe x8, 10GbE SFP+ ports and 1GbE RJ45, SATA. It's early access hardware, so it may have some pain points. Normal units will be available from the end of the year for $750. If I would have time and money right now, that's what I would buy.

It's only pre-order right now, and the firmware isn't done. They promise SBSA compliance (which includes ECAM PCIe working via a generic ACPI attachment) but they haven't passed the full test suite yet. Some experts are skeptical about whether full compliance is possible on that NXP chip…

I hope the PCIe works fine. And I hope the firmware will be FOSS like on their MACCHIATObin.

One thing they revealed is that the chip is overclockable (including memory), which is awesome. IIRC they got 2.5ish GHz core clock working. Would be amazing if it does like 3GHz with a voltage boost. (I don't expect software voltage control… but there's always hard mods :D)

Re: PCI Express on the Raspberry Pi 4

#64
post #41

Earlier quoted context omitted.

AArch64 is what the 64-bit version of the ARM instruction set is called.

ah right, think all software I use are available as AArch64 binaries.

You can get AArch64 in Amazon EC2 by the way… up to 16 A72 cores, which is nice.

Re: PCI Express on the Raspberry Pi 4

#65
post #56

Earlier quoted context omitted.

You could just use an USB device for higher throughput. The Sandisk Extreme Go, for example, is basically a small SSD in a USB drive form-factor.

If I’m reading it right, don’t you give up USB to get this PCIe access?

Bet the broadcom SoC has a USB controller built in, but unused... You could hook it up?

Re: PCI Express on the Raspberry Pi 4

#66
post #2

That's really cool. I'm curious, would it be possible to use a modern GPU (running at 1x) on an ARM based board? Would the open source drivers that are part of the Kernel work out the box on ARM?

NVIDIA drivers might even work too Linux 32-bit ARM drivers https://www.nvidia.co.uk/Download/driverResults.aspx/137468/...

This would be incredible if gotten to work with a pi. I've been eyeing the Jetson Nano, but if I could use a pi with a V100, that would be hilarious. And awesome.

Re: PCI Express on the Raspberry Pi 4

#67
post #55

Nice work! Would this be compatible with an M.2 to PCIe adaptor? [1] Being able to attach an Intel 660P and get 2 TB of fast SSD storage on a Raspberry Pi would be sweet. [1] https://www.amazon.com/EZDIY-FAB-Express-Adapter-Support-221...

Technically yes, but it's only a PCIe 1x Gen2 slot, so only 500MB/s of bandwidth (4x Gen3 is ~4GB/s). You'd be better off with a USB 3.0 to M.2 adapter.

The bandwidth works out about the same, but the USB controller and AHCI controllers will add quite some latency (and CPU load).

I'd like to see benchmarks, but my guess is single-thread random 4k read performance will more than double via PCI Express rather than the USB.

Re: PCI Express on the Raspberry Pi 4

#68
post #59

Earlier quoted context omitted.

Exactly, the PCIe reference clock is "only" 100MHz. USB 2.0 runs at 480MHz and motherboards have used 0.1" headers for them since the beginning.

While the ref clock is only 100MHz the data rate of PCI Express is much higher, it's a serial bus pushing multiple gigabits a second https://electronics.stackexchange.com/a/259002

Yes, the theoretical maximum (nyquist freq) of PCIe 4 is 8ghz

Re: PCI Express on the Raspberry Pi 4

#69
post #6

Earlier quoted context omitted.

Hack’s creator here - it’s on my list of things to try. GPUs are notoriously hard to get to work on non-intel, having tried to get a few up on Alpha and Itaniums in the past. VideoBIOS expects to run and expects a well behaving Intel CPU to do the power-up. That said X can sometimes emulate these quite well. On ARM we’d also run into alignment issues and likely other quirks - but in principle...

VBIOS is often not necessary for running a GPU in the OS. The amdgpu driver can POST a GPU by itself just fine. Still… X86EmulatorPkg allows running an amd64 VBIOS in UEFI on an aarch64 machine :) AFAIK the bigger problem on embedded boards is half assed Synopsys Designware host controllers. I have a Radeon running on my Marvell MACCHIATObin, on FreeBSD even. But from what I've heard the Rockchip RK3399 has a worse v…

Could you clarify to me/give a short definition of BAR space? For obvious reasons it's a bit hard to search for :)

Re: PCI Express on the Raspberry Pi 4

#70

Earlier quoted context omitted.

VBIOS is often not necessary for running a GPU in the OS. The amdgpu driver can POST a GPU by itself just fine. Still… X86EmulatorPkg allows running an amd64 VBIOS in UEFI on an aarch64 machine :) AFAIK the bigger problem on embedded boards is half assed Synopsys Designware host controllers. I have a Radeon running on my Marvell MACCHIATObin, on FreeBSD even. But from what I've heard the Rockchip RK3399 has a worse v…

Could you clarify to me/give a short definition of BAR space? For obvious reasons it's a bit hard to search for :)

In PCI, BAR is Base Address Register, which is a register in the PCI device's configuration space which defines where in the machine's physical memory address space that particular window of memory and/or I/O will be mapped (a single device can have several BARs, for instance a simple graphics card could have one for its control registers and one for the framebuffer). So the "BAR space" would be a shorthand for "the region of the physical memory address space which can be used to map the PCI devices memory through their Base Address Registers". The size of this region is limited, and graphics cards in particular tend to have somewhat large BARs.

(See for yourself in your machine: run "lspci -v", the lines starting with "Memory at ..." or "I/O ports at ..." are the BARs.)

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