MIPS R3000 • Hacker News Board

Re: MIPS R3000

#31

Post by alain94040 » Thu, Jun 20, 2019, 6:53 PM UTC

AnaniasAnanas wrote: post #30

opencl wrote: post #5

MIPS is a fun architecture (other than the delay slots that plagued early RISC ISAs) and implementing a subset of it on an FPGA is still a pretty common undergraduate university course project. I was kind of amazed just how simple it is to get a basic CPU working, though even the 1988 version was quite a lot more sophisticated than the class project version (multiple cache levels, having an MMU, probably much better…

Why does everyone seem to hate delay slots? I understand that it makes writing assembly more annoying but most people use a compiler anyway.

It makes the hardware implementation more complicated. The delay slot was perfect for the 5-pipeline original design. Once you try to push this to out of order execution (executing more than one instruction per cycle), the delay slot just doesn't make any sense.

Re: MIPS R3000

#32

Post by benwen » Thu, Jun 20, 2019, 6:54 PM UTC

cwt137 wrote: post #19

I remember reading a computer architecture book that used a fictional MIPS instruction set and used washing and drying clothes as an example of how to pipeline / do parallel instructions. Does anyone remember the name of that book?

Maybe Computation Structures by Ward? Lecture notes for the class from which it was born show a two-stage Laundromat model (with snarky MIT/Harvard humor) https://ocw.mit.edu/courses/electrical-engineering-and-compu...

Re: MIPS R3000

#33

Post by ajross » Thu, Jun 20, 2019, 6:54 PM UTC

AnaniasAnanas wrote: post #30

opencl wrote: post #5

MIPS is a fun architecture (other than the delay slots that plagued early RISC ISAs) and implementing a subset of it on an FPGA is still a pretty common undergraduate university course project. I was kind of amazed just how simple it is to get a basic CPU working, though even the 1988 version was quite a lot more sophisticated than the class project version (multiple cache levels, having an MMU, probably much better…

Why does everyone seem to hate delay slots? I understand that it makes writing assembly more annoying but most people use a compiler anyway.

They make writing assembly more annoying. They make writing compilers more annoying.

But the big reason is that except for the case of simple, short pipeline designs like the early MIPS parts they make designing CPUs annoying too.

The second you introduced parallel decode or a branch predictor with more than a cycle of latency these things hurt and don't help.

Re: MIPS R3000

#34

Post by monocasa » Thu, Jun 20, 2019, 6:57 PM UTC

pkaye wrote: post #28

monocasa wrote: post #21

Earlier quoted context omitted.

Alpha is bae. PowerPC is great as long as you don't look at the fever dream nightmare that is it's supervisor state.

Alpha had a weakly-ordered memory model though.

Yeah, but it wasn't that big of a deal in practice. I sort of like that it was such a weak memory model that you just explicitly had to synchronize any sorts of cross thread comms.

Re: MIPS R3000

#35

Post by messe » Thu, Jun 20, 2019, 7:01 PM UTC

PopePompus wrote: post #23

I'm honestly confused - why is a wikipedia page about an old computer architecture on the front page of HN?

Why wouldn't it be on the front of HN?

Re: MIPS R3000

#36

Post by kristopolous » Thu, Jun 20, 2019, 7:05 PM UTC

monocasa wrote: post #21

pinewurst wrote: post #2

It's still my favorite RISC processor and the only one that I actually liked coding in assembler (SPARC wasn't fun at all).

Alpha is bae. PowerPC is great as long as you don't look at the fever dream nightmare that is it's supervisor state.

Want one? I've got a 600mhz sitting in the cost. Totally works. I'm in Los Angeles

Re: MIPS R3000

#37

Post by aap_ » Thu, Jun 20, 2019, 7:05 PM UTC

mepian wrote: post #7

pinewurst wrote: post #2

It's still my favorite RISC processor and the only one that I actually liked coding in assembler (SPARC wasn't fun at all).

How annoying were the branch delay slots?

From having read lots of disassembled MIPS code I can tell you that they become second nature very quickly.

Re: MIPS R3000

#38

Post by naves » Thu, Jun 20, 2019, 7:05 PM UTC

segfaultbuserr wrote: post #3

Alternative history time: what if MIPS R4000 hasn't been killed by Pentium? Would we be running R10000-compatibles now?

We would be all now asking ourselves: What if Pentium hasn’t been killed by MIPS R4000?

Re: MIPS R3000

#39

Post by jawnv6 » Thu, Jun 20, 2019, 7:09 PM UTC

AnaniasAnanas wrote: post #30

opencl wrote: post #5

MIPS is a fun architecture (other than the delay slots that plagued early RISC ISAs) and implementing a subset of it on an FPGA is still a pretty common undergraduate university course project. I was kind of amazed just how simple it is to get a basic CPU working, though even the 1988 version was quite a lot more sophisticated than the class project version (multiple cache levels, having an MMU, probably much better…

Why does everyone seem to hate delay slots? I understand that it makes writing assembly more annoying but most people use a compiler anyway.

in addition to the complexities they add to every layer of the stack that ajross and alain94040 brought up, they're not all that useful in practice. i seem to recall that they'd rarely be over 50% utilized and the majority of instructions in the delay slot were nops

Re: MIPS R3000

#40

Post by cr0sh » Thu, Jun 20, 2019, 7:09 PM UTC

opencl wrote: post #5

MIPS is a fun architecture (other than the delay slots that plagued early RISC ISAs) and implementing a subset of it on an FPGA is still a pretty common undergraduate university course project. I was kind of amazed just how simple it is to get a basic CPU working, though even the 1988 version was quite a lot more sophisticated than the class project version (multiple cache levels, having an MMU, probably much better…

> I was kind of amazed just how simple it is to get a basic CPU working