Earlier quoted context omitted.
There are rumors that AMD is not happy with TR2's memory performance as the 4 channel memory controller is the bottleneck, they are probably looking at 8 channel memory option for TR3. ;)
Ha well I wouldn’t complain if they did that. The higher core count TR2s have a bit of a weird performance profile because of the memory channel setup - two of the chiplets have to hop through another chiplet for memory accesses. Is that what you’re referring to?
yes, they had to introduce that extra hop to workaround the fact that it has 4 less channel compared to the regular 8 channel EPYC.