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Amazon’s Chips Threaten Intel

nytimes.com

311–320 of 359 posts

Re: Amazon’s Chips Threaten Intel

#311
post #283

Earlier quoted context omitted.

Compare Amazon's (at least network) pricing to Google Cloud or Azure and its roughly competitive. The scale of the networks these companies are building is unlike any of the novice-level stuff companies like Hetzner deploy. As one example, in one region AWS has deployed 5 Pbps of inter-AZ fiber. They build all of their own SDN switches/routers, all the way down to the chips now, for maximum performance and configurat…

GCP is a real contender for potentially less money. It’s better than AWS in some if not many verticals. So I wouldn’t say AWS is “the best” (definitely not in the UI and user-friendliness department)

GCP is not nearly as good from my personal experience when it comes to support and reliability of services at scale. There are certainly some instances where GCP is easier to use, or they offer certain niche services that aren't exactly the same with AWS. Additionally given how close the costs are to begin with, it would very likely depend on your workloads as to which service was cheaper.

Overall I'd say Azure is the only real competition to AWS as a product (where they are often the most willing to negotiate a big deal), but googles open source efforts potentially pose a risk.

Re: Amazon’s Chips Threaten Intel

#312
post #235

Earlier quoted context omitted.

Just like it doesn't have a native Win32 environment, rather different personalities built on top of a common layer. UNIX environment on Windows is just like how IBM and Unisys mainframes deal with it.

Indeed. (Except that "WSL" should be read as "Windows Substitute for Linux.")

I don't remember FreeBSD or illumos calling their syscall compatibility layer for Linux Substitute.

Re: Amazon’s Chips Threaten Intel

#313
post #58

Earlier quoted context omitted.

So is AMD (they're shutting down GloFlo).

Source? GloFo stopped pursuing 7nm but that is far from shutting down.

Everyone working on R&D either got laid off, or moved to sustaining engineering on existing nodes. AMD is doing 7nm on TSMC. That's about as shut down as foundries get since the capital investment is all up front.

Re: Amazon’s Chips Threaten Intel

#314

Earlier quoted context omitted.

>"As cores get bigger the extra effort involved in handling the x86 ISA gets proportionally smaller." Can you elaborate on what you mean here? Do you mean as the number of cores gets bigger? Surely the size of the cores has been shrinking no? >"Of course Intel has traditionally always used their volume to be ahead in process technology" What's the correlation between larger volumes and quicker advances in process tec…

When RISC was first introduced its big advantage was that by reducing the number of instructions it could handle the whole processor could be fit onto a single chip whereas CISC chips took multiple chips. In the modern day it takes a lot more transistors and power to decode 4 x86 instructions in one cycle than 4 RISC instructions because you know the RISC instruction are going to start on bytes 0, 4, 8, and 12 wherea…

Thanks for the thorough detailed reply, I really appreciate it. I failed to grasp one thing you mentioned which is:

>"is actually an issue and that's part of why you don't see BIG.little approaches in x86 land and why atom did so poorly in the phone market."

Is BIG an acronym here? I had trouble understanding that sentence. Cheers.

Re: Amazon’s Chips Threaten Intel

#315

Earlier quoted context omitted.

Might you or anyone else be able to recommend a book or some literature on business and logistical side of third party chip design like this? Maybe something with some case studies?

Here's a free one that should cover what you're asking about. https://www.semiwiki.com/forum/content/4729-free-fabless-tra...

This is a great resource. Thanks. Cheers.

Re: Amazon’s Chips Threaten Intel

#316

Earlier quoted context omitted.

Could you or someone else elaborate on the different type of licenses and why a company interested in licensing might opt for one over another? I was surprised by the OPs comment that few companies actually license microarchitecture as I thought that's what Apple has been doing with ARM.

It is what Apple has been doing with ARM, but as he said there's only about 10 companies doing this, compared to the hundreds (thousands?) who take the core directly from ARM. Even big players like Qualcomm seem to be moving to just requesting tweaks to the Cortex cores. It's much, much easier & cheaper to take the premade core rather than developing your own. But your own custom design gives you the ability to diffe…

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Re: Amazon’s Chips Threaten Intel

#317

Earlier quoted context omitted.

Could you or someone else elaborate on the different type of licenses and why a company interested in licensing might opt for one over another? I was surprised by the OPs comment that few companies actually license microarchitecture as I thought that's what Apple has been doing with ARM.

It is what Apple has been doing with ARM, but as he said there's only about 10 companies doing this, compared to the hundreds (thousands?) who take the core directly from ARM. Even big players like Qualcomm seem to be moving to just requesting tweaks to the Cortex cores. It's much, much easier & cheaper to take the premade core rather than developing your own. But your own custom design gives you the ability to diffe…

Your link is exactly what I was looking for. Thanks!

Re: Amazon’s Chips Threaten Intel

#318
post #38

Earlier quoted context omitted.

So is AMD (they're shutting down GloFlo).

I thought they spun it off?

They did, but recently GloFlo announced that they're stopping R&D on newer nodes and are switching purely to sustaining engineering.

Re: Amazon’s Chips Threaten Intel

#320
post #174

Earlier quoted context omitted.

Sure, but intel CISC instructions can do more, so in the end is a wash.

That's not the case. Only one of Skylake's decoders can translate complex x86 instructions. The other 4 are simple decoders, and can only transform a simple x86 instruction into a single µop. At most, Skylake's decoder can emit 5 µops per cycle.[1] 1. https://en.wikichip.org/wiki/intel/microarchitectures/skylak...

... so what? most code's hot and should be issued from the uop cache at 6uop/cl with "80%+ hit rate" from your source

you're really not making the case that "decode" is the bottleneck, are you unaware of the mitigations that x86 designs have taken to alleviate that? or are those mitigations your proof that the ISA's deficient

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