AMD Discloses Initial Zen 2 Details • Hacker News Board

Re: AMD Discloses Initial Zen 2 Details

#161

Post by Tuna-Fish » Mon, Nov 19, 2018, 10:36 AM UTC

dopenmoredope wrote: post #90

Scaevolus wrote: post #79

Earlier quoted context omitted.

PCIE 4.0 was just standardized last year, it's not surprising that Zen 2 won't support 5.0, which is expected to be introduced mid next year. Zen 2 will be the first CPUs supporting 4.0.

Release date for PCIe 5.0 is Q1 2019 Furthermore... On June 5th, 2018, the PCI SIG released version 0.7 of the PCIe 5.0 specification to its members. PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day https://www.plda.com/products/xpressrich5 and... Historically, the earliest adopters of a new PCIe specification generally begin…

> AMD had plenty of time to include PCIe 5.0 even in the Draft 0.7 stage which is pretty much the same as final draft/release, but decided not to.

... Just how long do you think it takes to make that kind of design changes? This requires a major change in silicon. It would have had to been done more than a year ago.

Re: AMD Discloses Initial Zen 2 Details

#162

Post by ploek » Mon, Nov 19, 2018, 10:43 AM UTC

tutanchamun wrote: post #157

zymhan wrote: post #96

Earlier quoted context omitted.

I was actually underwhelmed by the post, what exactly is the "pretty bold" change?

Seperating the analog logic (IO die) from the digital logic (CPU cores). Analog shrinks really bad with smaller nodes wheras digital logic shrinks really good. New process nodes get more and more expensive - especially if the node is new (bad yields etc.) So you want to get the most out of it as possible, which AMD does with this strategy. For example Zen 1 8 core chips are 213 mm2 on 14nm. On 7nm these chipse would…

There is nothing analog about the IO die. It interfaces the memory, and the system's busses like PCIe. They are all digital.

Re: AMD Discloses Initial Zen 2 Details

#163

Post by ploek » Mon, Nov 19, 2018, 10:58 AM UTC

bpye wrote: post #64

tolien wrote: post #6

Earlier quoted context omitted.

Sort of - they let mainboard vendors decide whether to support it or not, which means it can be a crapshoot. For example, MSI's been known in the past to kill ECC support with a BIOS update; some vendors have tested that you can use ECC RAM but won't enable any of the error correction (for example, Gigabyte say this in [1]: "non-ECC mode".) Selfishly I really wish they would make it easier, because I'm in the market…

Asrock have been good in my experience at enabling all features on their boards. Back when Intel's Vt-d support depended on your board they reliably had support, and I believe they support ECC on all their new AMD boards.

I have ECC working on an AB350M Pro4. See also https://www.hardwarecanucks.com/forum/hardware-canucks-revie... The 'edac_mce_amd' module needs to be loaded on Linux.

Re: AMD Discloses Initial Zen 2 Details

#164

Post by Kipters » Mon, Nov 19, 2018, 11:11 AM UTC

apexalpha wrote: post #155

ahoka wrote: post #145

Earlier quoted context omitted.

LV2 is invite only on Azure, eg. not generally available.

Off-topic but eg = for example, ie = in other words.

Thanks, as a non native speaker this is very useful for me

Re: AMD Discloses Initial Zen 2 Details

#165

Post by m_eiman » Mon, Nov 19, 2018, 11:34 AM UTC

apexalpha wrote: post #155

ahoka wrote: post #145

Earlier quoted context omitted.

LV2 is invite only on Azure, eg. not generally available.

Off-topic but eg = for example, ie = in other words.

Both those are from Latin; I knew what e.g. is short for, but now I got around to looking up i.e. too:

ie => id est => that is

eg => exempli gratia => for example

Re: AMD Discloses Initial Zen 2 Details

#166

Post by atq2119 » Mon, Nov 19, 2018, 11:41 AM UTC

jacquesm wrote: post #159

atq2119 wrote: post #156

Earlier quoted context omitted.

I assume that should be " and can hide latency"? While GPU offloading is extremely powerful in terms of compute, you have to deal with both bandwidth limitations (de facto ~12 GB/s for x16 PCIe 3.0) and the latency of launching compute kernels and waiting for them to complete.

That depends on the problem space. For some problems latency does not need to be an issue, if the problem can be pipe-lined then you can keep all your cores running at a high percentage of their theoretical maximum load even if latency is high. For real time applications this is usually not an option, there latency > some threshold will kill your proposed solution.

In those cases where the latency is not a problem, it tends to be precisely because you can hide it e.g. via pipelining :)

Re: AMD Discloses Initial Zen 2 Details

#167

Post by tutanchamun » Mon, Nov 19, 2018, 11:44 AM UTC

ploek wrote: post #162

tutanchamun wrote: post #157

Earlier quoted context omitted.

Seperating the analog logic (IO die) from the digital logic (CPU cores). Analog shrinks really bad with smaller nodes wheras digital logic shrinks really good. New process nodes get more and more expensive - especially if the node is new (bad yields etc.) So you want to get the most out of it as possible, which AMD does with this strategy. For example Zen 1 8 core chips are 213 mm2 on 14nm. On 7nm these chipse would…

There is nothing analog about the IO die. It interfaces the memory, and the system's busses like PCIe. They are all digital.

Sorry, I've meant analog circuitry, which I've read again and again about on CPUs - see below as one example. And it was also mentioned in some articles about the IO die on Zen 2.

> Intel’s analog designers are responsible for creating circuits such as PLLs (for clocking) and PCIe (for I/O) that are critical for modern SoCs on a process that isn’t optimized for analog

https://www.realworldtech.com/intel-22ffl-process/

Re: AMD Discloses Initial Zen 2 Details

#168

Post by gmueckl » Mon, Nov 19, 2018, 11:47 AM UTC

atq2119 wrote: post #158

gmueckl wrote: post #142

Earlier quoted context omitted.

The hardware raytracing support is a huge step in the right direction for real time graphics. The shaky jenga tower of hacks on top of the rasterization pipeline that is in the current generation of rendering engines is barely sustainable. Fast raytracing provides an alternative that is much closer to the actual physical model of light transport in the real world and does not require as many nasty approximations and…

The currently available generation of hardware based real time raytracing cannot beat the quality of rasterization at the same framerates . NVidia built a cool bit of hardware, but their media blitz was seriously misleading. It's much faster than anything you can do on earlier hardware, but that doesn't mean it's actually fast yet for general game engines. One of the problems is that raytracing is inherently noisy, s…

I personally know some of the guys who developed the CNN based denoising. This stuff really works and it is actually pretty simple to implement compared to the truly horribly complicated hacks that you need to get e.g. realtime reflections even remotely to a level that is not outright jarring and obviously wrong looking.

What has me worried is not the performance of the ray-scene intersection, but the dynamic BVH update that is required for each frame. Building acceleration structures for ray intersection tests is a hard tradeoff between fast construction times and fast intersection tests. With animated/deforming objects, this is quite an interesting challenge. But we might eventually see some dedicated hardware for that, too. Academic implementations exist.

Re: AMD Discloses Initial Zen 2 Details

#169

Post by Tuna-Fish » Mon, Nov 19, 2018, 11:48 AM UTC

djsumdog wrote: post #47

I hope AMD has something on their video chip line-up against nVidia as well. I'm curious if they knew nVidia was working on ray-tracing and plan to implement the same API or if they have some other tech they have up their sleeve they've been working on vendors with. I hate how nVidia has such a monopoly on the video chip market. Who knows, maybe Intel will finally get back into the gamer 3D market and we might finall…

I find it unlikely that AMD would be able to release a proper peer competitor to nVidia's best any time soon.

Prior to the Ryzen launch, AMD lived through some really lean years. They saved wherever they could, and their GPU department saw very little investment on development for a long period. Since then, they have recapitalized the department, and are probably designing a proper next gen GPU architecture to replace GCN. However, it takes ~4-5 years to get a completely new arch on the market, and they only got to start a few years ago. Vega and Navi are both still shoestring budget designs.

Re: AMD Discloses Initial Zen 2 Details

#170

Post by Tuna-Fish » Mon, Nov 19, 2018, 12:00 PM UTC

bpye wrote: post #62

snuxoll wrote: post #16

Earlier quoted context omitted.

Threadripper’s 4 die variant had to be “neutered” to remain compatible with the TR4 socket without splitting memory bandwidth. The new I/O chiplet would solve that issue entirely, assuming it comes to Threadripper 3.

I was just thinking this. Yes it'll have half the lanes of EPYC still, okay, but now the lanes will be connected to all the dies equally rather than to just 1/2 the dies. This hopefully means Threadripper 3 can perform almost as well as EPYC with just 1/2 the memory bandwidth - that isn't insignificant but it's a big improvement on Threadripper 2.

An interesting point is that TR owners are much more likely to run their RAM at higher, out of JEDEC spec speeds, so the difference can be a lot smaller than 1/2.