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AMD Discloses Initial Zen 2 Details

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Re: AMD Discloses Initial Zen 2 Details

#71

Post by blattimwind »

mbell wrote: post #54

Anyone know why we aren't seeing Intel/AMD go the 'ultra-wide' route that we've seen in ARM processors? (Apple's in particular) e.g. we've seen Apple's A12 processor expand ALU's from 4->6 and what seems like a strong focus on cache latency and these changes seem to be rather beneficial in real code. Why aren't we seeing the same from Intel / AMD? As someone whom isn't particularly well informed on the topic my guess…

Intel cores have had eight EU ports since Haswell. Zen has a split pipeline, so it's not comparable. Zen has ten units, some µops use multiple EUs (e.g. AGU and ALU).

Re: AMD Discloses Initial Zen 2 Details

#72

Post by 0x8BADF00D »

coder543 wrote: post #66
s3cur3 wrote: post #21

Earlier quoted context omitted.

They did a follow up changing the scheduling policy for thread 0 (again, still on Windows) and it didn’t make a difference for almost all their workloads: https://www.anandtech.com/show/13446/the-quiz-on-cpu-0-playi...

AnandTech really needs to hire a Linux-focused editor to do some benchmarks there too, especially for these large systems that are unlikely to be running Windows anyways. The Phoronix benchmarks are quite clear,[0] I don't know why you keep linking to AnandTech's Windows benchmarks. I say this as someone who reads tons of AnandTech reviews because they're great, but Windows just doesn't do well with high core count h…

This seems like a familiar issue I've run into with workstations I've used in the past running Xeons. Not sure how NTOSKRNL handles scheduling of parallel tasks. I'd venture a guess and say it's hybrid (M:N threads), where multiple userland application threads are mapped to some "virtual processor" in kernelmode. That leads to priority inversion between the userland and kernelmode threads, which could explain why Windows benchmarks are terrible when dealing with multiple physical cores.

Re: AMD Discloses Initial Zen 2 Details

#73

Post by dopenmoredope »

astrodust wrote: post #41
beatgammit wrote: post #12

This is a pretty bold change and really makes Intel chips less appealing. With the recent kernel changes for Intel's Spectre issues and this chip coming up, I think it's a distinct possibility that AMD will take back a ton of marketshare in the server space. If these chips really do have a ~25% performance gain over Ryzen (not counting IPC gains), I might just upgrade, and I think a lot of other people are in the sam…

What's disappointing is that none of the major cloud vendors has made any real commitments to AMD, at least none that I've seen. If speculative execution is a problem and you need to give each VM its own exclusive cores, great when you can source parts with 64+ cores on them!

What's even more disappointing is that Zen 2 doesn't include support for new techs like the upcoming DDR5 & PCIe 5.0 which seems are going to be supported in Zen 4

https://www.anandtech.com/show/13578/naples-rome-milan-zen-4...

IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides?

MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change.

IC: So one might assume that an intercept might occur with Zen 4?

MP: No comment (!)

Re: AMD Discloses Initial Zen 2 Details

#74

Post by ChuckMcM »

"Oh the places you'll go" :-)

Assuming this chip doesn't trip all over itself moving things around, it will be an astonishing amount of computer power in a reasonably sized package. This is for me, the only reason to work at an internet giant; because they will build a tricked out motherboard with two sockets and up to 8TB of RAM and with say a petabyte of attached non-volatile storage available, field solvers, CFD apps, EM analysis would just melt away. Whether it is designing a rocket engine, or folding a protein, or annealing a semiconductor on the quantum level. So often these programs use approximations to allow them to run in finite time, and now more and more of the approximations are replaced with exact numerical solutions making the models more and more accurate.

Five years from now when people are throwing out these machines to replace them with Zen3 or Zen4 machines, I'm going to be super glad to get one and play with it.

Re: AMD Discloses Initial Zen 2 Details

#75

Post by monocasa »

mehrdadn wrote: post #39
blattimwind wrote: post #20

Earlier quoted context omitted.

Windows can use more than 64 hardware threads, but a single process kinda can't.

I think it can? https://msdn.microsoft.com/en-us/library/windows/desktop/dd4...

The KAFFITY in the GROUP_AFFINITY struct is a bitmap ULONG, so 64 bits on 64 bit archs, and 32 bits on 32 bit archs.

Re: AMD Discloses Initial Zen 2 Details

#76

Post by pjmlp »

screye wrote: post #51
djsumdog wrote: post #47

I hope AMD has something on their video chip line-up against nVidia as well. I'm curious if they knew nVidia was working on ray-tracing and plan to implement the same API or if they have some other tech they have up their sleeve they've been working on vendors with. I hate how nVidia has such a monopoly on the video chip market. Who knows, maybe Intel will finally get back into the gamer 3D market and we might finall…

I hate the Cuda monopoly in machine learning right now. I hope some of the mature libraries (TF, Pytorch) start officially supporting AMD GPUs. Nvidia is looting customers that want to use GPUs for Machine Learning on the cloud (like AWS, GCP)

Khronos is to blame by focusing too much on C, without convient tooling.

CUDA had C, C++ and Fortran support since the early days, followed by the PTX bytecode format for any compiler vendor that wanted to support CUDA on their languages.

It was necessary to loose the race for them to focus on C++ and come up with SPIR and SYSCL.

And tools still seem not to be on par with what NVidia offers.

Re: AMD Discloses Initial Zen 2 Details

#77

Post by mehrdadn »

monocasa wrote: post #75
mehrdadn wrote: post #39

Earlier quoted context omitted.

I think it can? https://msdn.microsoft.com/en-us/library/windows/desktop/dd4...

The KAFFITY in the GROUP_AFFINITY struct is a bitmap ULONG, so 64 bits on 64 bit archs, and 32 bits on 32 bit archs.

Yes but that means every group is 64 CPUs. Notice you can set affinity for any group (16-bit index).

Re: AMD Discloses Initial Zen 2 Details

#78

Post by esotericn »

tolien wrote: post #6
throwaway2048 wrote: post #5

Earlier quoted context omitted.

All AMD processors have supported ECC for a very long time, its trivial to support it, Intel have just decided to gate it as a premium feature.

Sort of - they let mainboard vendors decide whether to support it or not, which means it can be a crapshoot. For example, MSI's been known in the past to kill ECC support with a BIOS update; some vendors have tested that you can use ECC RAM but won't enable any of the error correction (for example, Gigabyte say this in [1]: "non-ECC mode".) Selfishly I really wish they would make it easier, because I'm in the market…

If it helps, I have a Gigabyte Designare X399 EX and it has full ECC support (have 64GB installed at the moment, edac-util checks out).

It is TR4 though. I grabbed a 1920X after the price drops.

Re: AMD Discloses Initial Zen 2 Details

#79

Post by Scaevolus »

dopenmoredope wrote: post #73
astrodust wrote: post #41

Earlier quoted context omitted.

What's disappointing is that none of the major cloud vendors has made any real commitments to AMD, at least none that I've seen. If speculative execution is a problem and you need to give each VM its own exclusive cores, great when you can source parts with 64+ cores on them!

What's even more disappointing is that Zen 2 doesn't include support for new techs like the upcoming DDR5 & PCIe 5.0 which seems are going to be supported in Zen 4 https://www.anandtech.com/show/13578/naples-rome-milan-zen-4... IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides? M…

PCIE 4.0 was just standardized last year, it's not surprising that Zen 2 won't support 5.0, which is expected to be introduced mid next year.

Zen 2 will be the first CPUs supporting 4.0.

Re: AMD Discloses Initial Zen 2 Details

#80

Post by pgeorgi »

fierarul wrote: post #34
Rychard wrote: post #8

Earlier quoted context omitted.

I recall hearing that certain motherboard manufacturers were disabling ECC for their lower-end AMD boards. Does anyone know if this was ever confirmed or not?

My newly purchased Gigabyte B450M DS3H, says clearly 'Dual Channel Non-ECC Unbuffered DDR4, 4 DIMMs'. https://www.gigabyte.com/us/Motherboard/B450M-DS3H-rev-10#kf It also mentions that: >Support for ECC Un-buffered DIMM 1Rx8/2Rx8 memory modules (operate in non-ECC mode) Note the operate in non-ECC mode remark. Seems pretty clear to me. The CPU might allow ECC but now it's the motherboard playing tricks.

playing tricks as in not routing the extra lines
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