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AMD Discloses Initial Zen 2 Details

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Re: AMD Discloses Initial Zen 2 Details

#81

Post by shaklee3 »

Scaevolus wrote: post #79
dopenmoredope wrote: post #73

Earlier quoted context omitted.

What's even more disappointing is that Zen 2 doesn't include support for new techs like the upcoming DDR5 & PCIe 5.0 which seems are going to be supported in Zen 4 https://www.anandtech.com/show/13578/naples-rome-milan-zen-4... IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides? M…

PCIE 4.0 was just standardized last year, it's not surprising that Zen 2 won't support 5.0, which is expected to be introduced mid next year. Zen 2 will be the first CPUs supporting 4.0.

Power9 was the first to support it over a year ago. But you're right, 5 is not finalized, so it's not possible for amd to support it.

Re: AMD Discloses Initial Zen 2 Details

#82

Post by majewsky »

ChuckMcM wrote: post #74

"Oh the places you'll go" :-) Assuming this chip doesn't trip all over itself moving things around, it will be an astonishing amount of computer power in a reasonably sized package. This is for me, the only reason to work at an internet giant; because they will build a tricked out motherboard with two sockets and up to 8TB of RAM and with say a petabyte of attached non-volatile storage available, field solvers, CFD a…

> exact numerical solutions

Isn't that an oxymoron? Numerical solutions always involve some sort of rounding errors because of limited floating-point precision, so they cannot be exact.

Re: AMD Discloses Initial Zen 2 Details

#83

Post by shaklee3 »

BeeOnRope wrote: post #68
djsumdog wrote: post #43

Earlier quoted context omitted.

Do the new 8th gen Intel chips finally deal with Spectre/Meltdown issues in hardware or do they still depend on OS level fixes?

8th gen (Coffee Lake) have the same uarch as Skylake and have no hardware fixes for Meltdown or Spectre.

And no pcie4 either, unfortunately.

Re: AMD Discloses Initial Zen 2 Details

#84

Post by shaklee3 »

BeeOnRope wrote: post #69
mbell wrote: post #54

Anyone know why we aren't seeing Intel/AMD go the 'ultra-wide' route that we've seen in ARM processors? (Apple's in particular) e.g. we've seen Apple's A12 processor expand ALU's from 4->6 and what seems like a strong focus on cache latency and these changes seem to be rather beneficial in real code. Why aren't we seeing the same from Intel / AMD? As someone whom isn't particularly well informed on the topic my guess…

Well AMD has gone wider - to 5 or 6 wide depending on how you count it in Ryzen. Intel hasn't really been able to make any changes to make any major uarch changes in years, since they've been stuck on Skylake (and all the various Skylake++ variants that followed which were Skylake in name only). In Skylake, most of the effort seemed focused on bringing AVX-512 to bear, and outside of that the basic design is largely…

Skylake also got rid of the ring core architecture, and went to the grid. That was a pretty drastic change, and very different from their previous generations.

Re: AMD Discloses Initial Zen 2 Details

#85

Post by ChuckMcM »

majewsky wrote: post #82
ChuckMcM wrote: post #74

"Oh the places you'll go" :-) Assuming this chip doesn't trip all over itself moving things around, it will be an astonishing amount of computer power in a reasonably sized package. This is for me, the only reason to work at an internet giant; because they will build a tricked out motherboard with two sockets and up to 8TB of RAM and with say a petabyte of attached non-volatile storage available, field solvers, CFD a…

> exact numerical solutions Isn't that an oxymoron? Numerical solutions always involve some sort of rounding errors because of limited floating-point precision, so they cannot be exact.

Reminds me of the mathematician joke, "We know that one side of one house is painted brown." :-)

You are correct in that most of these systems don't have a closed form solution that would yield an exact result, and they rely on either an interpolated value which is inexact depending on deviation or numerical solutions which typically iterate to the nearest point, that the system can represent in its limited 80 or 128 bit floating point system.

Re: AMD Discloses Initial Zen 2 Details

#86

Post by b1r6 »

ChuckMcM wrote: post #74

"Oh the places you'll go" :-) Assuming this chip doesn't trip all over itself moving things around, it will be an astonishing amount of computer power in a reasonably sized package. This is for me, the only reason to work at an internet giant; because they will build a tricked out motherboard with two sockets and up to 8TB of RAM and with say a petabyte of attached non-volatile storage available, field solvers, CFD a…

I'm excited. My next build shall be AMD.

Re: AMD Discloses Initial Zen 2 Details

#87

Post by Twirrim »

astrodust wrote: post #41
beatgammit wrote: post #12

This is a pretty bold change and really makes Intel chips less appealing. With the recent kernel changes for Intel's Spectre issues and this chip coming up, I think it's a distinct possibility that AMD will take back a ton of marketshare in the server space. If these chips really do have a ~25% performance gain over Ryzen (not counting IPC gains), I might just upgrade, and I think a lot of other people are in the sam…

What's disappointing is that none of the major cloud vendors has made any real commitments to AMD, at least none that I've seen. If speculative execution is a problem and you need to give each VM its own exclusive cores, great when you can source parts with 64+ cores on them!

AWS, Microsoft, Oracle, Packet... all have AMD shapes, in bare metal and VM to varying degrees. The list goes on and on.

Oracle: https://www.amd.com/en/press-releases/2018-10-23-amd-and-ora...

Azure: https://azure.microsoft.com/en-us/blog/announcing-the-lv2-se...

AWS: https://aws.amazon.com/about-aws/whats-new/2018/11/introduci...

Packet: https://www.packet.com/hardware/amd/

Re: AMD Discloses Initial Zen 2 Details

#88

Post by zdw »

The most interesting thing about this is the speculation about the I/O die being flexible enough to take other workloads - it's basically the "chipset" of old.

I wonder if they'll license it - with Apple's A12 already on the 7nm TSMC process, building a Xeon crushing ARM monster for the new Mac Pro by swapping the Ryzen dies for ARM dies seems like a great bit of leverage, assuming Cook and Su could arrange it.

Re: AMD Discloses Initial Zen 2 Details

#89

Post by atq2119 »

bpye wrote: post #64
tolien wrote: post #6

Earlier quoted context omitted.

Sort of - they let mainboard vendors decide whether to support it or not, which means it can be a crapshoot. For example, MSI's been known in the past to kill ECC support with a BIOS update; some vendors have tested that you can use ECC RAM but won't enable any of the error correction (for example, Gigabyte say this in [1]: "non-ECC mode".) Selfishly I really wish they would make it easier, because I'm in the market…

Asrock have been good in my experience at enabling all features on their boards. Back when Intel's Vt-d support depended on your board they reliably had support, and I believe they support ECC on all their new AMD boards.

I can confirm that ECC at least works for their Threadripper mainboards.

Re: AMD Discloses Initial Zen 2 Details

#90

Post by dopenmoredope »

Scaevolus wrote: post #79
dopenmoredope wrote: post #73

Earlier quoted context omitted.

What's even more disappointing is that Zen 2 doesn't include support for new techs like the upcoming DDR5 & PCIe 5.0 which seems are going to be supported in Zen 4 https://www.anandtech.com/show/13578/naples-rome-milan-zen-4... IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides? M…

PCIE 4.0 was just standardized last year, it's not surprising that Zen 2 won't support 5.0, which is expected to be introduced mid next year. Zen 2 will be the first CPUs supporting 4.0.

Release date for PCIe 5.0 is Q1 2019

Furthermore...

On June 5th, 2018, the PCI SIG released version 0.7 of the PCIe 5.0 specification to its members.

PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day

https://www.plda.com/products/xpressrich5

and...

Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources.

From here: https://en.wikipedia.org/wiki/PCI_Express

AMD had plenty of time to include PCIe 5.0 even in the Draft 0.7 stage which is pretty much the same as final draft/release, but decided not to.

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