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Question, why is DRAM still packed separately?
It might make more sense now that there are more types of memory-like storage which isn't quite as fast as DDR4, like Optane.
But reading between the lines, AMD is only showing benchmarks for extremely parallel loads much like they did with ThreadRipper 2. Between the physically separate processing cores and the nature of the marketing benchmarks, I suspect workloads that have high IPC or extremely low latency requirements won't fare so well on this chip.
The weirdest part is to think what Apple might come up with if they were to take the A12X design and connect it on a die like AMD has done here. It would probably make for a pretty interesting Mac Pro.
Earlier quoted context omitted.
RAID 6 with 32 drives. All the things you would not do while the array is rebuilding.
Why, RAID6 can rebuild online, because it turns temporarily into a RAID5. Even RAID5 can be used while rebuilding, in read-only mode, because data from the remaining disks is sufficient (else rebuilding won't be possible).
Earlier quoted context omitted.
RAID 6 with 32 drives. All the things you would not do while the array is rebuilding.
I aware of the issues one can have with rebuilding a large raid array. It seems like you will always hit some parity issue upon reconstruction. What is the proper approach here?
Question, why is DRAM still packed separately?
For higher power parts, heat dissipation is the primary reason. Most of the high end CPUs are purely heat limited in terms of performance. A TDP of 90W is about the limit for CPUs using cheap cooling techniques, and adding ram would lower that by 10-30W.
I keep reading that some data centers switch to liquid cooling, so likely it does. Maybe with advances on this front, we'll see the increase of the CPU efficiency that the fabrication process can no more deliver.
Working with a $399 threadripper motherboard that has four x16 physical slots, it can accommodate four Intel x710-4 10GbE four port NICs (each electrically x8), for a total of sixteen 10GbE router interfaces in a Linux kernel based FRR system, as a fully software implemented router. And with the RAM capacity of a 32GB system, no worries about FIB size. It's a very different approach to do with a routing entirely in CPU vs ASICs. But this can be built for under $4000.
Or one could just as easily use those four physical x16 slots for four independent 100GbE interfaces.
Question, why is DRAM still packed separately?
Additionally DRAM more or less has to be separate chips due to the sheer surface area for yield reasons. The amount of DRAM in a decent sized server is close to a whole wafer.
Question, why is DRAM still packed separately?
A different question is why is DRAM still colocated with the CPUs, and not centrally located over a very fast network? There was a company doing this (RNA Networks, founded 2006) which was sold to Dell and then apparently disappeared without trace. It might make more sense now that there are more types of memory-like storage which isn't quite as fast as DDR4, like Optane.
Question, why is DRAM still packed separately?
A different question is why is DRAM still colocated with the CPUs, and not centrally located over a very fast network? There was a company doing this (RNA Networks, founded 2006) which was sold to Dell and then apparently disappeared without trace. It might make more sense now that there are more types of memory-like storage which isn't quite as fast as DDR4, like Optane.
Not particularly related to Rome, but what you can buy right now for a single socket system, AMD is far ahead of Intel for reasonably priced workstations or small servers with a huge amount of I/O. One threadripper CPU has 64 pci express 3.0 lanes. One lane is 985MB/s. Working with a $399 threadripper motherboard that has four x16 physical slots, it can accommodate four Intel x710-4 10GbE four port NICs (each electri…
I suspect there might never be one so as not to muddy the waters of Epyc's intended market.