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Open source RISC-V implemented from scratch in one night

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Re: Open source RISC-V implemented from scratch in one night

#21

Post by _chris_ »

leibwiht wrote: post #20
exikyut wrote: post #17

I wonder how easy it would be to port https://github.com/xoreaxeaxeax/sandsifter to the RISC-V instruction set. Would probably be a decent step in the right direction for validating/verifying the future of trusted computing. Although... this gives rise to a 2nd thought. If it was _this easy_ to build a RISC-V implementation, is it all that special, technically speaking? I ask as someone naive about processor design.…

My understanding of sandsifter is that it works by executing an instruction next to a page boundary, which gives either a page fault error (the instruction executed correctly and then execution passed over to the next page which is presumably non-executable) or an error indicating the instruction was malformed. So, for it to work on RISC-V you need paging, and also interrupt vectors to work. The MMU was only recently…

Sandsifter is dealing with the problem of "how do I find valid instructions in any 1-15 byte sequence, which yields 2^120 combinations?"

In RISC-V there are currently only 2 byte and 4 byte instructions, which you can brute force your way through. The specification does technically allow for longer sequences, in which case sandsifter will work just fine. [And the RISC-v privileged specification has existed for years].

Re: Open source RISC-V implemented from scratch in one night

#22

Post by Erlich_Bachman »

moetech wrote: post #14
inetknght wrote: post #7

Earlier quoted context omitted.

"Modern" desktop computing is perhaps less resource hungry than you think when you cut away so much graft of telemetry. None or barely few games, of course. But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text? I think it's very achievable.

The web is incredibly bloated unfortunately. I had to upgrade my RAM recently because I couldn't open too many browser tabs without making the system hang, even with javascript disabled. Apart from that, you can do almost everything from the command line so even an old Raspberry Pi could be usable as a desktop computer.

You could still have a lot of RAM with RISC-V. The web does require lots of RAM nowadays, yes. But it is not a problem in this regard.

Re: Open source RISC-V implemented from scratch in one night

#23

Post by bem94 »

Whoa. This is very impressive!

It does seem to hilight an increasing unease I have with riscv. Implementations are many and cheap, but reusable verification is rare and people don't use what is out there. They have maybe the riscv-tests set working. But that's not enough to call your new CPU usable for anything other than a hobby project.

Fwiw, the riscv-formal package from Clifford wolf is the closest thing to a turn key solution to verifying a riscv core, even if people must remember it doesn't cover everything.

Re: Open source RISC-V implemented from scratch in one night

#24

Post by yipbub »

trumped wrote: post #12
lisk1 wrote: post #10

As the possibilities for smaller transistor get narrower companies will get more open towards smaller clients with small budgets, so taping out homebrew CPUs or SOCs or integrated circuits will be possible.

so far, the opposite is happening in the "cellphone"/pocket pc space... it is getting hard to get a phone that you can root without having to resort to "holes" that can get patched at any time...

Can you elaborate please?

Re: Open source RISC-V implemented from scratch in one night

#26

Post by h4b4n3r0 »

moetech wrote: post #14
inetknght wrote: post #7

Earlier quoted context omitted.

"Modern" desktop computing is perhaps less resource hungry than you think when you cut away so much graft of telemetry. None or barely few games, of course. But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text? I think it's very achievable.

The web is incredibly bloated unfortunately. I had to upgrade my RAM recently because I couldn't open too many browser tabs without making the system hang, even with javascript disabled. Apart from that, you can do almost everything from the command line so even an old Raspberry Pi could be usable as a desktop computer.

Take a look at Tab Wrangler extension. It closes tabs you haven’t used in a while.

Re: Open source RISC-V implemented from scratch in one night

#27

Post by cmrx64 »

leibwiht wrote: post #20
exikyut wrote: post #17

I wonder how easy it would be to port https://github.com/xoreaxeaxeax/sandsifter to the RISC-V instruction set. Would probably be a decent step in the right direction for validating/verifying the future of trusted computing. Although... this gives rise to a 2nd thought. If it was _this easy_ to build a RISC-V implementation, is it all that special, technically speaking? I ask as someone naive about processor design.…

My understanding of sandsifter is that it works by executing an instruction next to a page boundary, which gives either a page fault error (the instruction executed correctly and then execution passed over to the next page which is presumably non-executable) or an error indicating the instruction was malformed. So, for it to work on RISC-V you need paging, and also interrupt vectors to work. The MMU was only recently…

> The MMU was only recently standardized so I'm not sure if it's actually implemented in any hardware or software yet, but once you have those two things it should be fairly straightforward

Chips with MMUs have been taped out for years. Likewise the Linux port has existed for years.

Re: Open source RISC-V implemented from scratch in one night

#28

Post by renox »

_chris_ wrote: post #19
exikyut wrote: post #17

I wonder how easy it would be to port https://github.com/xoreaxeaxeax/sandsifter to the RISC-V instruction set. Would probably be a decent step in the right direction for validating/verifying the future of trusted computing. Although... this gives rise to a 2nd thought. If it was _this easy_ to build a RISC-V implementation, is it all that special, technically speaking? I ask as someone naive about processor design.…

RISC-V is pretty nice in that the ISA gets out of your way, and you can focus on the techniques to build a high-performance processor without wasting effort on legacy and other weird corner case behaviors. A++, would recommend. However, if you want to build really high performance cores, there are plenty of challenging techniques you have to employ that add a lot of complexity that is hidden below the ISA abstraction…

> RISC-V is pretty nice in that the ISA gets out of your way

Except for the C variant where they went to 110% complexity for maximum ICache efficiency: 32bit instructions aligned to 16bit?? I wonder if there are other RISC ISA which made the same choice.

Re: Open source RISC-V implemented from scratch in one night

#29

Post by deeesa1 »

Impressive, I like this! I'm curious more in general how widely risc-v is being used in the industry today already (they mentioned a steep adoption from academia to industry). Looking at the foundation members, there are quite a big number; given they range for risc-v is from small devices to super computers, are there any examples where it's used today and showed benefits over other archs?

Re: Open source RISC-V implemented from scratch in one night

#30

Post by Annatar »

"The main motivation for the darkriscv is create a migration path for some projects around the 680x0/coldfire family."

On the Amiga we don't need a replacement for MC680## processors because we have the Vampire 2+ accelerator, which gives us a superscalar, 64-bit MC68080 with AMMX extensions.

Coming to ATARI ST and Amiga 1200 near you if the Apollo team keeps this momentum.

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