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Open source RISC-V implemented from scratch in one night

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Re: Open source RISC-V implemented from scratch in one night

#11

Post by xmo »

kbumsik wrote: post #8

I don't know anything about RISC-V ISA yet, but I am wondering if its ISR is great for learning computer architecture in shcools compared to MIPS, the dominant ISR at colleges for introductory computer architecture classes? The HDL (Verilog) code looks quite short and simple. If the partial implementation of the ISR implementation is like that it shouldn't be so bad for learning...

Yes. Berkeley started using it to teach introductory computer architecture: http://www-inst.eecs.berkeley.edu/~cs61c/sp18/

A major project of the course is to build RISVC emulator and implement 2-stage pipeline in logisim.

Re: Open source RISC-V implemented from scratch in one night

#12

Post by trumped »

lisk1 wrote: post #10

As the possibilities for smaller transistor get narrower companies will get more open towards smaller clients with small budgets, so taping out homebrew CPUs or SOCs or integrated circuits will be possible.

so far, the opposite is happening in the "cellphone"/pocket pc space... it is getting hard to get a phone that you can root without having to resort to "holes" that can get patched at any time...

Re: Open source RISC-V implemented from scratch in one night

#14

Post by moetech »

inetknght wrote: post #7
earenndil wrote: post #2

This is good news for risc-v! The fact that it can be implemented so easily by hobbyists furthers the cause of trusted hardware. Sure, it won't be implementable by hobbyists at the speeds necessary for modern desktop computing, but a trusted security core (something like a yubikey) could be implemented on completely from-scratch hardware, but then still use existing trusted/vetted software (openssl), just a cross-com…

"Modern" desktop computing is perhaps less resource hungry than you think when you cut away so much graft of telemetry. None or barely few games, of course. But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text? I think it's very achievable.

The web is incredibly bloated unfortunately. I had to upgrade my RAM recently because I couldn't open too many browser tabs without making the system hang, even with javascript disabled. Apart from that, you can do almost everything from the command line so even an old Raspberry Pi could be usable as a desktop computer.

Re: Open source RISC-V implemented from scratch in one night

#15

Post by kbumsik »

xmo wrote: post #11
kbumsik wrote: post #8

I don't know anything about RISC-V ISA yet, but I am wondering if its ISR is great for learning computer architecture in shcools compared to MIPS, the dominant ISR at colleges for introductory computer architecture classes? The HDL (Verilog) code looks quite short and simple. If the partial implementation of the ISR implementation is like that it shouldn't be so bad for learning...

Yes. Berkeley started using it to teach introductory computer architecture: http://www-inst.eecs.berkeley.edu/~cs61c/sp18/ A major project of the course is to build RISVC emulator and implement 2-stage pipeline in logisim.

Well Berkeley would certainly wants to teach RISC-V since Berkeley made that architecture. But it is still great to see they are actually using it in classes!

Re: Open source RISC-V implemented from scratch in one night

#16

Post by geomark »

oddity wrote: post #4
josemanuel wrote: post #3

Writing RTL takes one night but, how long will the verification take? How much will it take to tapeout? Who will pay for it?

As someone living in hardware land, I have a lot of respect for all the effort that goes into those steps of the process and I’m glad you brought it up, but presumably they aren’t that important to the point of a hobby project like this.

Another hardware lander here. Did a lot of verification of processors in the past, including one that was Mips-like. Parent comment is correct in its suggestion that verification is a much bigger deal than getting HDL that will compile and pass a few test cases. But for a hobby project, yeah, no need to throw a wet blanket on it.

Re: Open source RISC-V implemented from scratch in one night

#17

Post by exikyut »

I wonder how easy it would be to port https://github.com/xoreaxeaxeax/sandsifter to the RISC-V instruction set.

Would probably be a decent step in the right direction for validating/verifying the future of trusted computing.

Although... this gives rise to a 2nd thought. If it was _this easy_ to build a RISC-V implementation, is it all that special, technically speaking? I ask as someone naive about processor design. Is implementation relatively straightforward, but design hard?

Re: Open source RISC-V implemented from scratch in one night

#18

Post by henrikeh »

xmo wrote: post #11
kbumsik wrote: post #8

I don't know anything about RISC-V ISA yet, but I am wondering if its ISR is great for learning computer architecture in shcools compared to MIPS, the dominant ISR at colleges for introductory computer architecture classes? The HDL (Verilog) code looks quite short and simple. If the partial implementation of the ISR implementation is like that it shouldn't be so bad for learning...

Yes. Berkeley started using it to teach introductory computer architecture: http://www-inst.eecs.berkeley.edu/~cs61c/sp18/ A major project of the course is to build RISVC emulator and implement 2-stage pipeline in logisim.

The technical university of Denmark also transistioned to teaching computer arch using RISC-V. Some of the most popular textbooks are also being converted to RISC-V editions.

Re: Open source RISC-V implemented from scratch in one night

#19

Post by _chris_ »

exikyut wrote: post #17

I wonder how easy it would be to port https://github.com/xoreaxeaxeax/sandsifter to the RISC-V instruction set. Would probably be a decent step in the right direction for validating/verifying the future of trusted computing. Although... this gives rise to a 2nd thought. If it was _this easy_ to build a RISC-V implementation, is it all that special, technically speaking? I ask as someone naive about processor design.…

RISC-V is pretty nice in that the ISA gets out of your way, and you can focus on the techniques to build a high-performance processor without wasting effort on legacy and other weird corner case behaviors. A++, would recommend.

However, if you want to build really high performance cores, there are plenty of challenging techniques you have to employ that add a lot of complexity that is hidden below the ISA abstraction layer (speculation for example).

So if you want to make RISC-V go fast, you have to employ more design tricks like "macro-op fusion". For example, scan for two load instructions in the fetch stream and fuse them into a single "load-pair" micro-op if they access adjacent addresses. There are a whole bag of tricks like this that are irrespective of the ISA and add a fairly high "skill-ceiling" to processor design.

Re: Open source RISC-V implemented from scratch in one night

#20

Post by leibwiht »

exikyut wrote: post #17

I wonder how easy it would be to port https://github.com/xoreaxeaxeax/sandsifter to the RISC-V instruction set. Would probably be a decent step in the right direction for validating/verifying the future of trusted computing. Although... this gives rise to a 2nd thought. If it was _this easy_ to build a RISC-V implementation, is it all that special, technically speaking? I ask as someone naive about processor design.…

My understanding of sandsifter is that it works by executing an instruction next to a page boundary, which gives either a page fault error (the instruction executed correctly and then execution passed over to the next page which is presumably non-executable) or an error indicating the instruction was malformed. So, for it to work on RISC-V you need paging, and also interrupt vectors to work. The MMU was only recently standardized so I'm not sure if it's actually implemented in any hardware or software yet, but once you have those two things it should be fairly straightforward.
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