Open source RISC-V implemented from scratch in one night
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Re: Open source RISC-V implemented from scratch in one night
#2Re: Open source RISC-V implemented from scratch in one night
#3Re: Open source RISC-V implemented from scratch in one night
#4Writing RTL takes one night but, how long will the verification take? How much will it take to tapeout? Who will pay for it?
Re: Open source RISC-V implemented from scratch in one night
#5Writing RTL takes one night but, how long will the verification take? How much will it take to tapeout? Who will pay for it?
The posters intention is not to start producing hardware, at no point does his project mention taping it out and manufacturing. Obviously it is just a fun side project to implement the RISC-V core ISA in an FGA. It was then made open-source on GitHub so anyone else interested can look at it. Chill out mate.
Re: Open source RISC-V implemented from scratch in one night
#6Writing RTL takes one night but, how long will the verification take? How much will it take to tapeout? Who will pay for it?
Obviously more than a night, but hey development is completely open so you can see for yourself.
> How much will it take to tapeout?
0 days. It is running on an FPGA.
> Who will pay for it?
See previous comment. Presumably the author paid for the FPGA, but maybe it was a gift?
Re: Open source RISC-V implemented from scratch in one night
#7This is good news for risc-v! The fact that it can be implemented so easily by hobbyists furthers the cause of trusted hardware. Sure, it won't be implementable by hobbyists at the speeds necessary for modern desktop computing, but a trusted security core (something like a yubikey) could be implemented on completely from-scratch hardware, but then still use existing trusted/vetted software (openssl), just a cross-com…
None or barely few games, of course. But word processing, email, and pure HTML browsing without javascript? Maybe not HTML5's fancy features, but general rich text?
I think it's very achievable.
Re: Open source RISC-V implemented from scratch in one night
#8The HDL (Verilog) code looks quite short and simple. If the partial implementation of the ISR implementation is like that it shouldn't be so bad for learning...
Re: Open source RISC-V implemented from scratch in one night
#9I don't know anything about RISC-V ISA yet, but I am wondering if its ISR is great for learning computer architecture in shcools compared to MIPS, the dominant ISR at colleges for introductory computer architecture classes? The HDL (Verilog) code looks quite short and simple. If the partial implementation of the ISR implementation is like that it shouldn't be so bad for learning...