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Darpa invests $100M in a silicon compiler

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Re: Darpa invests $100M in a silicon compiler

#251

Post by civilitty »

gricardo99 wrote: post #228
usmannk wrote: post #120

Earlier quoted context omitted.

I think a reasonable explanation may be that other customers possibly have come to unknowingly rely on some of the bugs. Shipping a fix of all the bugs could actually break their code!

That’s absolutely true. Once you’ve delivered hardware with certain bugs that can be worked around by firmware/software, often that means the firmware/software teams don’t need or even want those bugs fixed. Fixing the bug means they’d have to go back and change their workarounds, which not only costs time/money, but adds risk that their may be unintended consequences and new issues.

Yep, there is a method to the madness. Something complex like making an electronic product is bound to have tons of pitfalls and most of these behaviors have rational (albeit twisted by economic incentive) reasons for why the things are the way they are.

We were, however, an established client of Qualcomm and working on a new design so we explicitly asked for all bug fixes and they refused except for the ones we could name. We got "lucky" in that no other client had needed both bug fixes at the same time and when the build system broke, the one guy responsible for it was MIA so we got the whole source dump (they didn't even test their fixes together until a client found problems).

I've used other Qualcomm products with different engineering support teams that are much better at source control, testing, and even devops but it's a very rare sight within the industry.

Re: Darpa invests $100M in a silicon compiler

#252

Post by WalterBright »

rch wrote: post #238
ptrott2017 wrote: post #216

Earlier quoted context omitted.

Walter - appears Xilinx are the current copyright holder and ABEL was last supported in the XILINX 10.1 ISE toolset released circa 2008 (Current release is 14.7). Introductory guide can still be found here: https://bit.ly/2NfkLWq

This is the URL behind the shortened link: https://www.xilinx.com/support/documentation/sw_manuals/xili...

Thanks, I'll contact them and see what they have to say.

Re: Darpa invests $100M in a silicon compiler

#253

Post by thomastjeffery »

0x00000000 wrote: post #109
rickycook wrote: post #97

Earlier quoted context omitted.

and why do they have to? in australia we have CSIRO which does some amazing research, and our military budget is basically non existent compared to the US military budget

Australian defense budget is 36 billion [1] with a GDP of 1.2 trillion. US defense budget is 600 billion with a GDP of 18 trillion. It is just about the exact same percent of GDP. [1] https://www.pyneonline.com.au/media-centre/media-releases/a-...

And it's $700bn now, which is almost as much as the entire rest of the world spends on defense.

GDP is not what that defense budget is protecting. People and property are what that budget exists to protect.

China has the second highest defense budget. We have about 1/4 the population of China, yet we spend several times more on defense.

Re: Darpa invests $100M in a silicon compiler

#254

Post by ur-whale »

st26 wrote: post #249
ur-whale wrote: post #186

Earlier quoted context omitted.

You're saying the problem is harder. I'm more than willing to believe that. Wouldn't you then want ten times the number of people eyeballing the code? And boatloads of free contributers submitting change requests to fix potential problems? And a marketplace of users that can freely choose deciciding which "IP (I still find the term so deeply offensive, I can't help but it I have to put it in quote)?

The key is the solution is so application specific. Write code once, it runs anywhere forever more. But IP blocks are not really like that. Especially advanced IP (USB1.1 vs USB3.1) need to be heavily customized for each application. So John user can't just download a block from Sourceforge and use it.

"sourceforge". nuff said.

Re: Darpa invests $100M in a silicon compiler

#255

Post by Karrot_Kream »

st26 wrote: post #249
ur-whale wrote: post #186

Earlier quoted context omitted.

You're saying the problem is harder. I'm more than willing to believe that. Wouldn't you then want ten times the number of people eyeballing the code? And boatloads of free contributers submitting change requests to fix potential problems? And a marketplace of users that can freely choose deciciding which "IP (I still find the term so deeply offensive, I can't help but it I have to put it in quote)?

The key is the solution is so application specific. Write code once, it runs anywhere forever more. But IP blocks are not really like that. Especially advanced IP (USB1.1 vs USB3.1) need to be heavily customized for each application. So John user can't just download a block from Sourceforge and use it.

A lot of very complicated, distributed systems require a lot of customization and tuning to run. Kafka, a system used for distributed "logging" (sorry for the gloss) is known to have a huge operational burden, and takes a lot of customization. If you've ever deployed ElasticSearch, a document search tool, you know you have to write non-trivial blocks of code that operate on the domain of the target documents, to even have ElasticSearch produce basic results.

The point is that, while these blocks can be complicated and need lots of customization, the ability to grab the source and modify it yourself is a huge enabler. If I could grab a stock IP from a repo and then spend 40 man-hours customizing it, it would be a huge benefit over spending 1000 man-hours making the IP from scratch.

I hate to appeal to expertise, but I've written HDL, synthesized it, and done mask layouts before. I understand that it requires a lot of customizing, but the first step to all of this is sharing. Sharing infrastructural components is a huge reason of why the commodity software business is as robust as it is.

Re: Darpa invests $100M in a silicon compiler

#256

Post by st26 »

Karrot_Kream wrote: post #255
st26 wrote: post #249

Earlier quoted context omitted.

The key is the solution is so application specific. Write code once, it runs anywhere forever more. But IP blocks are not really like that. Especially advanced IP (USB1.1 vs USB3.1) need to be heavily customized for each application. So John user can't just download a block from Sourceforge and use it.

A lot of very complicated, distributed systems require a lot of customization and tuning to run. Kafka, a system used for distributed "logging" (sorry for the gloss) is known to have a huge operational burden, and takes a lot of customization. If you've ever deployed ElasticSearch, a document search tool, you know you have to write non-trivial blocks of code that operate on the domain of the target documents, to even…

I don't disagree that it would be great & all. But there's things working against it, that software doesn't really have to deal with (or at least has solved) is my point.

And let's be honest, a state of the art block ported to the latest process isn't going to be 40 man-hours to customize, you're probably looking at more like a couple man-years unless it's very well designed... Which is why reusable core shops are a viable business. And how vibrant of an open source community would you have, if it took a small team a year just to customize & implement the open source design to their application? You would have very few users.

Now, you could argue that because a lot of the real work is in the customization that they could open source the core. But where does the customization end, and the core, the root functionality begin?

I think a more realistic pitch would be an open source testbench or behavioral model that verifies your core is fully spec compliant.

Re: Darpa invests $100M in a silicon compiler

#257

Post by cottonseed »

ur-whale wrote: post #191
zik wrote: post #155

I'm surprised to see no recognition of yosys, arachne-pnr and the icestorm tools which together are a free and open source HDL tool chain which already exists and is pretty widely used.

These two projects are exactly the road the EDA industry should be taking. Unfortunately, they make very slow progress because they have to painstakingly reverse-engineer everything (with the possible exception of Lattice stuff). For Xilinx chips, where exactly nothing is publicly documented at the lower levels of the stack, they have to spend mountains of time re-discovering everything. Even if I deeply admire the e…

> with the possible exception of Lattice stuff > For Xilinx chips, where exactly nothing is publicly documented at the lower levels of the stack, they have to spend mountains of time re-discovering everything.

The situation with Lattice parts was the same; they reverse engineered them.

Re: Darpa invests $100M in a silicon compiler

#258

Post by 437598735 »

ur-whale wrote: post #191
zik wrote: post #155

I'm surprised to see no recognition of yosys, arachne-pnr and the icestorm tools which together are a free and open source HDL tool chain which already exists and is pretty widely used.

These two projects are exactly the road the EDA industry should be taking. Unfortunately, they make very slow progress because they have to painstakingly reverse-engineer everything (with the possible exception of Lattice stuff). For Xilinx chips, where exactly nothing is publicly documented at the lower levels of the stack, they have to spend mountains of time re-discovering everything. Even if I deeply admire the e…

Note I don't work at Xilinx. And be prepared that what I'm about to write may seem incredibly cynical, sorry.

But if I were to take a guess at why the culture is the way it is, I'd say that it's because programmable logic is fundamentally relatively small logic tiles replicated across large areas.

That means across competing companies there's a high chance for infringing upon arsenals of patents for rather mundane things like interconnect, logic families, or memory cell layout where there are only a handful of viable alternatives yet the patent offices were likely duped into accepting multiple legalese interpretations of the same underlying tech. It's a minefield.

Xilinx is not really a chip manufacturing business either. They're fabless. Imagine having a company that designs RAM memory and outsources everything beyond the cell design. If you don't own the foundry itself you're not going to last very long unless you encrypt the memory access protocols, obfuscate your (probably patent infringing) hardware architecture by layers of undocumented tooling, and dominate the industry by buying up any upcoming contenders while cross-licensing stuff to build up a complex ecosystem of interdependent tools required to get even the most basic project done.

Re: Darpa invests $100M in a silicon compiler

#259

Post by hollerith »

jandrese wrote: post #161
hollerith wrote: post #100

Earlier quoted context omitted.

I don't disagree with your post, but you shouldn't use the Zumwalt class as an example because the US has decided to stop production of it after 3 ships. For a citation see the bottom of the section https://en.wikipedia.org/wiki/Zumwalt-class_destroyer#Backgr...

I don't think the Zumwalt was ever meant to be a mass production ship. I think it was built the prove the concept of lower signature vessels. Notably it's too small and lightly armed to accomplish most Navy objectives. The stealth technology makes it hard to modify for specific objectives. Basically, what are you going to do with a Zumwalt that you couldn't do with a submarine? Is it better at any of those tasks than…

>>I don't think the Zumwalt was ever meant to be a mass production ship

You think wrong.

Re: Darpa invests $100M in a silicon compiler

#260

Post by mips_avatar »

bmcooley wrote: post #149
mips_avatar wrote: post #99

Earlier quoted context omitted.

The project I'm working on right now is with a FLIR tau 2 thermal camera. Our university got it donated but the only decent expansion board is 1400 euro so i figured I might use that budget to build my own. I basically just need to convert LVDS to mipi csi-2 or ethernet. You can find the LVDS spec on page 16 of this spec sheet https://www.flir.com/globalassets/imported-assets/document/f... I need to make a board with…

I'm curious, my uni satellite club is using the same camera for a cubesat, is that the same domain you're using it for?

We are building ours for a drone. Please feel free to contact me if you want to work together to figure this camera out.
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